IDTSTAC9751XXTAEC1XR IDT, Integrated Device Technology Inc, IDTSTAC9751XXTAEC1XR Datasheet - Page 20

• Manufacturer Part Number: IDTSTAC9751XXTAEC1XR
• Description: IC CODEC AC'97 2CH VALUE 48-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Audio Codec '97r

Specifications of IDTSTAC9751XXTAEC1XR

• Resolution (bits): 18 b, 20 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 85 / 89
• Voltage - Supply, Analog: 3.14 V ~ 3.47 V; 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 3.47 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: STAC9751XXTAEC1XR

4. AC-LINK
IDT™
VALUE-LINE TWO-CHANNEL AC’97 CODECS
STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS
4.1.
4.2.
Clocking
Reset
Figure 10 shows the AC-Link point to point serial interconnect between the STAC9750/9751 and its
companion controller. All digital audio streams and command/status information are communicated
over this AC-Link. See “Digital Interface” on page 21 for details.
STAC9750/9751 derives its clock internally from an externally connected 24.576 MHz crystal or an
oscillator, through the XTAL_IN pin. Synchronization with the AC'97 controller is achieved through
the BIT_CLK pin at 12.288 MHz.
The beginning of all audio sample packets, or “Audio Frames”, transferred over AC-Link is synchro-
nized to the rising edge of the “SYNC” signal driven by the AC'97 controller. Data is transitioned on
AC-Link on every rising edge of BIT_CLK, and subsequently sampled by the receiving side on each
immediately following falling edge of BIT_CLK.
There are 3 types of resets:
1. a “cold” reset where all STAC9750/9751 logic and registers are initialized to their default state
2. a “warm” reset where the contents of the STAC9750/9751 register set are left unaltered
3. a “register” reset which only initializes the STAC9750/9751 registers to their default states
After signaling a reset to the STAC9750/9751, the AC'97 controller should not attempt to play or cap-
ture audio data until it has sampled a “CODEC Ready” indication via register 26h from the
STAC9750/9751.
For proper reset operation SDATA_OUT should be 0 during cold reset.
D igital D C '97
C ontroller
A
Figure 10. AC-Link to its Companion Controller
SD AT A _O U T
SD AT A _IN
BIT _C LK
R ES E T#
S YN C
20
A C '97 C odec
STAC9750/9751
XT A L_IN
XT A L_O U T
PC AUDIO
V 5.8 103106