IDTSTAC9751XXTAEC1XR IDT, Integrated Device Technology Inc, IDTSTAC9751XXTAEC1XR Datasheet - Page 22

• Manufacturer Part Number: IDTSTAC9751XXTAEC1XR
• Description: IC CODEC AC'97 2CH VALUE 48-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Audio Codec '97r

Specifications of IDTSTAC9751XXTAEC1XR

• Resolution (bits): 18 b, 20 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 85 / 89
• Voltage - Supply, Analog: 3.14 V ~ 3.47 V; 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 3.47 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: STAC9751XXTAEC1XR

IDT™
VALUE-LINE TWO-CHANNEL AC’97 CODECS
STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS
5.1.1.
AC-Link Audio Output Frame (SDATA_OUT)
The audio output frame data streams correspond to the multiplexed bundles of all digital output data
targeting the STAC9750/9751 DAC inputs, and control registers. Each audio output frame supports
up to twelve 20-bit outgoing data time slots. Slot 0 is a special Reserved time slot containing 16 bits
that are used for AC-Link protocol infrastructure.
Within slot 0, the first bit is a global bit (SDATA_OUT slot 0, bit 15) which flags the validity for the
entire audio frame. If the “Valid Frame” bit is a 1, this indicates that the current audio frame contains
at least one slot time of valid data. The next 12 bit positions sampled by the STAC9750/9751 indi-
cate which of the corresponding 12 times slots contain valid data. In this way data streams of differ-
ing sample rates can be transmitted across AC-Link at its fixed 48 KHz audio frame rate. The
following diagram illustrates the time slot based AC-Link protocol.
A new audio output frame begins with a low to high transition of SYNC. SYNC is synchronous to the
rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, the STAC9750/9751
samples the assertion of SYNC. This following edge marks the time when both sides of AC-Link are
aware of the start of a new audio frame. On the next rising edge of BIT_CLK, the AC'97 controller
transitions SDATA_OUT into the first bit position of slot 0 (Valid Frame bit). Each new bit position is
presented to AC-Link on a rising edge of BIT_CLK, and subsequently sampled by the STAC9750/
9751 on the following falling edge of BIT_CLK. This sequence ensures that data transitions, and
subsequent sample points for both incoming and outgoing data streams, are time aligned.
OUTGOING STREAMS
SDATA_OUT
INCOMING STREAMS
BIT_CLK
End of previous audio frame
SYNC
TAG PHASE
Figure 11. AC'97 Standard Bi-directional Audio Frame
12.288 MHz
SYNC
Frame
valid
Figure 12. AC-Link Audio Output Frame
slot1
Tag Phase
slot2
("1" = time slot contains valid PCM data)
Time Slot "Valid" Bits
slot(12)
TAG
TAG
STATUS
"0"
CMD
ADR
ADR
22
CID1 CID0
STATUS
DATA
CMD
DATA
LEFT
LEFT
PCM
PCM
19
Slot 1
PCM
PCM
RT
RT
"0"
NA
NA
DATA PHASE
19
Slot 2
PCM
CTR
NA
20.8 uS (48 kHZ)
STAC9750/9751
Data Phase
LSURR
"0"
RSVD
PCM
19
RSURR
RSVD
PCM
Slot 3
RSVD
PCM
LFE
"0"
RSVD
PCM
LALT
19
RALT
RSVD
PCM
PC AUDIO
Slot 12
V 5.8 103106
RSVD
RSVD
"0"