ADV601LCJST Analog Devices Inc, ADV601LCJST Datasheet
ADV601LCJST
Specifications of ADV601LCJST
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ADV601LCJST Summary of contents
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FEATURES 100% Bitstream Compatible with the ADV601 Precise Compressed Bit Rate Control Field Independent Compression 8-Bit Video Interface Supports CCIR-656 and Multi- plexed Philips Formats General Purpose 16- or 32-Bit Host Interface with 512 Deep 32-Bit FIFO PERFORMANCE Real-Time ...
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ADV601LC TABLE OF CONTENTS This data sheet gives an overview of the ADV601LC functional- ity and provides details on designing the part into a system. The text of the data sheet is written for an audience with a general knowledge ...
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INTERNAL ARCHITECTURE The ADV601LC is composed of eight blocks. Three of these blocks are interface blocks and five are processing blocks. The interface blocks are the Digital Video I/O Port, the Host I/O Port, and the external DRAM manager. The ...
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ADV601LC THE WAVELET KERNEL This block contains a set of filters and decimators that work on the image in both horizontal and vertical directions. Figure 6 illustrates the filter tree structure. The filters apply carefully chosen wavelet basis functions that ...
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Figure 4. Unfiltered Original Image (Analog Devices Corporate Offices, Norwood, Massachusetts) REV. 0 Figure 5. Modified Mallat Diagram of Image –5– ADV601LC ...
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ADV601LC LUMINANCE AND COLOR COMPONENTS (EACH SEPARATELY) HIGH LOW PASS IN PASS HIGH LOW PASS IN PASS IN BLOCK HIGH LOW HIGH PASS IN PASS IN ...
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THE PROGRAMMABLE QUANTIZER This block quantizes the filtered image based on the response profile of the human visual system. In general, the human eye cannot resolve high frequencies in images to the same level of accuracy as lower frequencies. Through ...
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ADV601LC Table II. ADV601LC Typical Quantization of Mallat Data 1 Block Data Mallat Bin Width Blocks Factors 39 0x007F 40 0x009A 41 0x009A 36 0x00BE 33 0x00BE 30 0x00E4 34 0x00E6 35 0x00E6 37 0x00E6 38 0x00E6 31 0x0114 32 ...
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REGISTER ADDRESS BYTE 3 RESERVED 0x0 RESERVED 0x4 0x8 RESERVED 0xC INDIRECT (INTERNALLY INDEXED) REGISTERS {ACCESS THESE REGISTERS THROUGH THE INDIRECT REGISTER ADDRESS AND INDIRECT REGISTER DATA REGISTERS} *NOTE: YOU MUST WRITE 0X0880 TO THE MODE CONTROL REGISTER ON CHIP ...
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ADV601LC ADV601LC REGISTER DESCRIPTIONS Indirect Address Register Direct (Write) Register Byte Offset 0x00. This register holds a 16-bit value (index) that selects the indirect register accessible to the host through the indirect data register. All indirect write registers are 16 ...
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FIFO Error, FIFOERR. This condition indicates that the host has been unable to keep up with the ADV601LC’s compressed data supply or demand requirements. If this condition occurs during encode, the data stream will not be corrupted until MERR ...
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ADV601LC [5] Video Interface Master/Slave Mode Select, M/S. This bit selects the following: 0 Slave mode video interface (External control of video timing, HSYNC-VSYNC-FIELD are inputs), reset value 1 Master mode video interface (ADV601LC controls video timing, HSYNC-VSYNC are outputs) ...
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VIDEO AREA REGISTERS The area defined by the HSTART, HEND, VSTART and VEND registers is the active area that the wavelet kernel processes. Video data outside the active video area is set to minimum luminance and zero chrominance (black) by ...
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ADV601LC Sum of Squares [0–41] Registers Indirect (Read Only) Register Index 0x080 through 0x0A9 The Sum of Squares [0–41] registers hold values that correspond to the summation of values (squared) in corresponding Mallat blocks [0–41]. These registers let the Host ...
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MIN Cb Value Register Indirect (Read Only) Register Index 0x0AF The MIN Cb Value register lets the host or DSP read the minimum pixel value for the Cb component in the unprocessed data. The Host reads these values through the ...
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ADV601LC Clock Pins Name Pins I/O VCLK/XTAL 2 I VCLKO 1 O Video Interface Pins Name Pins I/O VSYNC HSYNC FIELD ENC 1 O VDATA[7:0] 8 I/O PIN ...
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DRAM Interface Pins Name Pins I/O DDAT[15:0] 16 I/O DADR[8: RAS 1 O CAS Host Interface Pins Name Pins I/O DATA[31:0] 32 I/O ADR[1: BE0–BE3 ...
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ADV601LC Host Interface Pins (Continued) Name Pins I/O ACK 1 O FIFO_SRQ 1 O STATS_R 1 O LCODE 1 O HIRQ 1 O RESET 1 I Power Supply Pins Name Pins I/O GND 16 I VDD 13 I Description Host ...
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Video Interface The ADV601LC video interface supports two types of compo- nent digital video (D1) interfaces in both compression (input) and decompression (output) modes. These digital video inter- faces include support for the Multiplexed Philips 4:2:2 and CCIR-656/SMPTE125M—international standard. Video ...
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ADV601LC Clocks and Strobes All video data is synchronous to the video clock (VCLK). The rising edge of VCLK is used to clock all data into the ADV601LC. Synchronization and Blanking Pins Three signals, which can be configured as inputs ...
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Video Formats — Multiplexed Philips Video The ADV601LC supports a hybrid mode of operation that is a cross between standard dual lane Philips and single lane CCIR- 656. In this mode, video data is multiplexed in the same fashion in ...
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ADV601LC Compressed Data-Stream Definition Through its Host Interface the ADV601LC outputs (during encode) and receives (during decode) compressed digital video data. This stream of data passing between the ADV601LC and the host is hierarchically structured and broken up into blocks ...
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Table XII. Pseudo-Code Describing a Sequence of Video Fields Complete Sequence: <Field 1 Sequence> <Field 2 Sequence> <Field 1 Sequence> <Field 2 Sequence> (Field Sequences) <Field 1 Sequence> <Field 2 Sequence> #EOS Field 1 Sequence: #SOF1 <VITC> <First Block Sequence> ...
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ADV601LC In general, a Frame of data is made up of odd and even Fields as shown in Figure 11. Each Field Sequence is made First Block Sequence and a Complete Block Sequence. The First Block Sequence ...
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Table XIII. Pseudo-Code of Compressed Video Data Bitstream for One Field of Video Block Sequence Data #SOFn<VITC><TYPE4><BW><Huff_Data> #SOB4<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB1<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB1<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB1<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB1<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB1<BW><Huff_Data> ...
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ADV601LC Table XV. ADV601LC Field and Block Delimiters (Codes) Code Name Code #SOF1 0xffffffff40000000 #SOF2 0xffffffff41000000 <VITC> (96 bits) <TYPE1> 0x81 <TYPE2> 0x82 <TYPE3> 0x83 <TYPE4> 0x84 #SOB1 0xffffffff81 #SOB2 0xffffffff82 #SOB3 0xffffffff83 #SOB4 0xffffffff84 #SOB5 0xffffffff8f Description (Align all ...
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Table XVI. ADV601LC Field and Block Delimiters (Codes) Code Name Code <BW> (16 bits, 8.8) <HUFF_DATA> (Modulo 32) #EOS 0xffffffffc0ffffff Table XVII. Video Data Bitstream for One Field In a Video Sequence ffff ffff 4000 0000 0000 8400 00ff df0c ...
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ADV601LC APPLYING THE ADV601LC This section includes the following topics: • Using the ADV601LC in computer applications • Using the ADV601LC in standalone applications • Configuring the host interface for 6- or 32-bit data paths • Connecting the video interface ...
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ADR1 ADR2 DATA0–7 DATA8-15 ADR0 ADSP-21csp01 CLKIN IOMS RD WR FLIN2 FLIN0 IRQ0 FLIN1 IOACK THE ADSP-21csp01 INTERNAL CLOCK RATE DOUBLE THE INPUT CLOCK *THE INPUT CLOCK RATE = 1/2 OF THE INTERNAL CLOCK RATE, RANGING FROM 12 TO 21MHz ...
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ADV601LC GETTING THE MOST OUT OF ADV601LC The unique sub-band block structure of luminance and color components in the ADV601LC offers many unique application benefits. Analog Devices will offer a Feature Software Library as well as separate feature application documentation ...
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SPECIFICATIONS The ADV601LC Video Codec uses a Bi-Orthogonal (7, 9) Wavelet Transform. RECOMMENDED OPERATING CONDITIONS Parameter Description V Supply Voltage DD T Ambient Operating Temperature AMB ELECTRICAL CHARACTERISTICS Parameter Description V Hi-Level Input Voltage IH V Lo-Level Input Voltage IL ...
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ADV601LC TEST CONDITIONS Figure 18 shows test condition voltage reference and device loading information. These test conditions consider an output as disabled when the output stops driving and goes from the measured high or low voltage to a high impedance ...
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VCLK (O) VCLKO (VCLK2 = 0) (I) VCLKO (VCLK2 = 1) NOTE: USE VCLK FOR CLOCKING VIDEO-ENCODE OPERATIONS AND USE VCLKO FOR CLOCKING VIDEO-DECODE OPERATIONS. DO NOT TRY TO USE EITHER CLOCK FOR BOTH ENCODE AND DECODE. CCIR-656 Video ...
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ADV601LC Figure 22. CCIR-656 Video—Line (Horizontal) and Frame (Vertical) Transfer Timing Note that for CCIR-656 Video—Decode and Master Line (Horizontal) timing, VDATA is synchronous with VCLKO. –34– REV. 0 ...
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Multiplexed Philips Video Timing The diagrams in this section show transfer timing for pixel (YCrCb) data in Multiplexed Philips video mode. For line (horizontal) and frame (vertical) data transfer timing, see Figure 25. All output values assume a maximum pin ...
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ADV601LC Figure 25. Multiplexed Philips Video–Line (Horizontal) and Frame (Vertical) Transfer Timing –36– REV. 0 ...
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Table XXV. Multiplexed Philips Video—Encode and Master Pixel (YCrCb) Timing Parameters Parameter Description t VDATA Bus, Encode Master Multiplexed Philips, Setup VDATA_EMM_S t VDATA Bus, Encode Master Multiplexed Philips, Hold VDATA_EMM_H t CTRL Signals, Encode Master Multiplexed Philips, Delay CTRL_EMM_D ...
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ADV601LC Host Interface (Indirect Address, Indirect Register Data, and Interrupt Mask/Status) Register Timing The diagrams in this section show transfer timing for host read and write accesses to all of the ADV601LC’s direct registers, except the Compressed Data register. Accesses ...
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Table XXVIII. Host (Indirect Address, Indirect Data, and Interrupt Mask/Status) Write Timing Parameters Parameter Description WR Signal, Direct Register, Write Cycle Time (at 27 MHz VCLK) t WR_D_WRC WR Signal, Direct Register, Pulsewidth Asserted (at 27 MHz VCLK) t WR_D_PWA ...
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ADV601LC Host Interface (Compressed Data) Register Timing The diagrams in this section show transfer timing for host read and write transfers to the ADV601LC’s Compressed Data register. Accesses to the Compressed Data register are faster than access timing for the ...
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Table XXX. Host (Compressed Data) Write Timing Parameters Parameter Description WR Signal, Compressed Data Direct Register, Write Cycle Time t WR_CD_WRC WR Signal, Compressed Data Direct Register, Pulsewidth Asserted t WR_CD_PWA WR Signal, Compressed Data Direct Register, Pulsewidth Deasserted t ...
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ADV601LC Pin Pin Pin Name Type 1 DATA4 I/O 2 DATA3 I/O 3 DATA2 I/O 4 DATA1 I/O 5 DATA0 I/O 6 VDD POWER 7 GND GROUND ADR1 I 12 ...
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DATA4 1 PIN 1 2 DATA3 IDENTIFIER DATA2 3 DATA1 4 DATA0 5 6 VDD GND ADR1 ADR0 12 13 GND BE2–BE3 14 BE0–BE1 15 GND 16 RESET 17 VDD 18 ACK ...
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... ADV601LC 0.030 (0.75) 0.025 (0.60) 0.018 (0.45) SEATING 0.003 (0.08) Part Number Ambient Temperature Range ADV601LCJST +70 C NOTES Commercial temperature range ( +70 C Plastic Thin Quad Flatpack. OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 120-Lead LQFP (ST-120) 0.638 (16.20) 0.630 (16.00) SQ 0.622 (15.80) ...