ADV601LCJST Analog Devices Inc, ADV601LCJST Datasheet - Page 19

• Manufacturer Part Number: ADV601LCJST
• Description: IC CODEC VIDEO DSP/SRL 120LQFP
• Manufacturer: Analog Devices Inc
• Type: Video Codecr

Specifications of ADV601LCJST

• Rohs Status: RoHS non-compliant
• Data Interface: DSP, Serial
• Resolution (bits): 8 b
• Sigma Delta: No
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 120-LQFP

Video Interface
The ADV601LC video interface supports two types of compo-
nent digital video (D1) interfaces in both compression (input)
and decompression (output) modes. These digital video inter-
faces include support for the Multiplexed Philips 4:2:2 and
CCIR-656/SMPTE125M—international standard.
Video interface master and slave modes allow for the generation
or receiving of synchronization and blanking signals. Definitions
for the different formats can be found later in this section. For
recommended connections to popular video decoders and
encoders, see the Connecting The ADV601LC To Popular Video
Decoders and Encoders section. A complete list of supported
video interfaces and sampling rates is included in Table V.
Name
CCIR-656
Multiplex
Internally, the video interface translates all video formats to one
consistent format to be passed to the wavelet kernel. This con-
sistent internal video standard is 4:2:2 at 16 bits accuracy.
VITC and Closed Captioning Support
The video interface also supports the direct loss-less extraction
of 90-bit VITC codes during encode and the insertion of VITC
codes during decode. Closed Captioning data (found on active
Video Line 21) is handled just as normal active video on an
active scan line. As a result, no special dedicated support is
necessary for Closed Captioning. The data rates for Closed
Captioning data are low enough to ensure robust operation of
this mechanism at compression ratios of 50:1 and higher. Note
that you must include Video Line 21 in the ADV601LC’s de-
fined active video area for Closed Caption support.
27 MHz Nominal Sampling
There is one clock input (VCLK) to support all internal process-
ing elements. This is a 50% duty cycle signal and must be syn-
chronous to the video data. Internally this clock is doubled using
a phase locked loop to provide for a 54 MHz internal processing
clock. The clock interface is a two pin interface that allows a
crystal oscillator to be tied across the pins or a clock oscillator to
drive one pin. The nominal clock rate for the video interface is
27 MHz. Note that the ADV601LC also supports a pixel rate of
13.5 MHz.
Video Interface and Modes
In all, there are seven programmable features that configure the
video interface. These are:
• Encode-Decode Control
• Master-Slave Control
REV. 0
Philips
In addition to determining what functions the internal pro-
cessing elements must perform, this control determines the
direction of the video interface. In decode mode, the video
interface outputs data. In encode mode, the interface receives
data. The state of the control is reflected on the ENC pin.
This pin can be used as an enable input by external line driv-
ers. This control is maintained by the host processor.
This control determines whether the ADV601LC generates or
Table V. Component Digital Video Interfaces
Bits/
Component Space
8
8
Color
YCrCb 4:2:2
YUV
Sampling Rate (MHz) I/F Width
4:2:2
Nominal
Date
27
27
8
8
–19–
• 525-625 (NTSC-PAL) Control
525-625
Control
0
1
• Bipolar/Unipolar Color Component
• Active Area Control
• Video Format
receives the VSYNC, HSYNC, and FIELD signals. In master
mode, the ADV601LC generates these signals for external
hardware synchronization. In slave mode, the ADV601LC
receives these signals. Note that some video formats require
the ADV601LC to operate in slave mode only. This control is
maintained by the host processor.
This control determines whether the ADV601LC is operating
on 525/NTSC video or 625/PAL video. This information is
used when the ADV601LC is in master and decode modes so
that the ADV601LC knows where and when to generate the
HSYNC, VSYNC, and FIELD Pulses as well as when to
insert the SAV and EAV time codes (for CCIR-656 only) in
the data stream. This control is maintained by the host pro-
cessor. Table VI shows how the 525-625 Control in the Mode
Control register works.
This mode determines whether offsets are used on color com-
ponents. In Philips mode, this control is usually set to Bipo-
lar, since the color components are normal twos-compliment
signed values. In CCIR-656 mode, this control is set to Uni-
polar, since the color components are offset by 128. Note that
it is likely the ADV601LC will function if this control is in the
wrong state, but compression performance will be degraded.
It is important to set this bit correctly.
Four registers HSTART (horizontal start), HEND (horizon-
tal end), VSTART (vertical start) and VEND (vertical end)
determine the active video area. The maximum active video
area is 720 by 288 pixels for a single field.
This control determines the video format that is supported. In
general, the goal of the various video formats is to support
glueless interfaces to the wide variety of video formats periph-
eral components expect. This control is maintained by the
host processor. Table VII shows a synopsis of the supported
video formats. Definitions of each format can be found later
in this section. For Video Interface pins descriptions, see the
Pin Function Descriptions.
Table VI. Square Pixel Control, 525-625 Control, and
Video Formats
Max
Horizontal
Size
720
720
Max
Field
Size
243
288
ADV601LC
NTSC-PAL
CCIR-601 NTSC
CCIR-601 PAL