ADV7202KST Analog Devices Inc, ADV7202KST Datasheet
ADV7202KST
Specifications of ADV7202KST
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ADV7202KST Summary of contents
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FEATURES Four 10-Bit Video DACs (4:2:2, YCrCb, RGB I/P Supported) 10-Bit Video Rate Digitization MHz AGC Control ( 6 dB) Front End 3-Channel Clamp Control Up to Five CVBS Input Channels, Two Component YUV, Three ...
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ADV7202–SPECIFICATIONS 5 V SPECIFICATIONS (AVDD/DVDD = 5 V Parameter STATIC PERFORMANCE_DAC Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity Differential Nonlinearity VIDEO ADC Resolution Accuracy Integral Nonlinearity Differential Nonlinearity 2 Input Voltage Range SNR AUX ADC Resolution Differential Nonlinearity Integral ...
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V SPECIFICATIONS (AVDD/DVDD = 5 V Parameter 1 POWER REQUIREMENTS AVDD/DVDD Normal Power Mode 2 I DAC 3 I DSC 4 I ADC 4 I ADC 5 Sleep Mode Current Power-Up Time 6 2 MPU PORT —I C SCLOCK ...
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ADV7202–SPECIFICATIONS 5 V SPECIFICATIONS (AVDD/DVDD = 4.75 V – 5. Parameter PROGRAMMABLE GAIN AMPLIFIER Video ADC Gain 3 CLAMP CIRCUITRY Clamp Fine Source/Sink Current Clamp Coarse Source/Sink Current 4 CLOCK CONTROL DACCLK0/DACCLK1 DACCLK1 DACCLK1 7 ...
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V SPECIFICATIONS (AVDD/DVDD = 3.3 V Parameter STATIC PERFORMANCE_DAC Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity Differential Nonlinearity VIDEO ADC Resolution Accuracy Integral Nonlinearity Differential Nonlinearity 2 Differential Input Voltage Range SNR AUX ADC Resolution Differential Nonlinearity Integral ...
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ADV7202–SPECIFICATIONS 3.3 V SPECIFICATIONS (AVDD/DVDD = 3.3 V Parameter 1 POWER REQUIREMENTS AVDD/DVDD Normal Power Mode 2 I DAC 3 I DSC 4 I ADC 5 Sleep Mode Current Power-Up Time 6 2 MPU PORT —I C SCLOCK Frequency SCLOCK ...
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V SPECIFICATIONS (AVDD/DVDD = 3.3 V Parameter PROGRAMMABLE GAIN AMPLIFIER Video ADC Gain 3 CLAMP CIRCUITRY Clamp Fine Source/Sink Current Clamp Coarse Source/Sink Current 4 CLOCK CONTROL DACCLK0/DACCLK1 DACCLK1 7 DACCLK1 Data Setup Time ...
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ADV7202 1 ABSOLUTE MAXIMUM RATINGS AVDD to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Pin No. Mnemonic 1 SYNC_IN 2 SCL 3 ALSB 4 XTAL0 5 XTAL1 6 AVDD_ADC 7 AVSS_ADC 8–19 AIN1–AIN6 20 DVSS 21 REFADC 22 CML 23, 24 CAP2, CAP1 25 OSDEN 26–35 DOUT[9:0] 36 OSDIN2 37 OSDIN1 38 OSDIN0 39 ...
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ADV7202 FUNCTIONAL DESCRIPTION Analog Inputs The ADV7202 has the capability of sampling up to five CVBS video input signals, two component YUV, or three S-Video inputs. Eight auxiliary general-purpose inputs are also available. Table I shows the analog signal input ...
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VIDEO CLAMPING AND AGC CONTROL When analog signal clamping is required, the input signal should be ac-coupled to the input via a capacitor, the clamping control is via the MPU port. The AGC is implemented digitally. For cor- rect operation, ...
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ADV7202 XTAL0 DOUT [9:0] SYNC_OUT Figure 3. SYNC_OUT Output Timing, YCrCb Input MPU PORT DESCRIPTION The ADV7202 supports a 2-wire serial (I microprocessor bus driving multiple peripherals. Two inputs, serial data (SDA) and serial clock (SCL), carry information between any ...
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WRITE S SLAVE ADDR SEQUENCE LSB = 0 READ S SLAVE ADDR SEQUENCE S = START BIT P = STOP BIT t 3 SDA SCL DACCLK1 13 DATA [9:0] DATA DACCLK0 Figure 8. Input Data Format Timing ...
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ADV7202 DIGITAL DATA INPUT TIMING DIAGRAMS A0 DACCLK1 DACCLK0 DAC_DATA [9:0] DAC0 Figure 10. DAC Mode 1, Single Clock, Single Edge Input Data Format Timing Diagram* *The figure shows three DAC usages. DACCLK0 is a data line that indicates the ...
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XTAL0 DOUT [9:0] Figure 14. Standard Mode Digital Data O/P Format REGISTER ACCESS The MPU can write to or read from all of the registers of the ADV7202 except the Subaddress Registers, which are write-only. The Subaddress Register determines which ...
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ADV7202 MODE REGISTER 0 MR0 (MR07–MR00) (Address (SR4–SR0) = 00H) Figure 16 shows the various operations under the control of Mode Register 0. MR0 BIT DESCRIPTION ADC Reference Voltage (MR00) This control bit is used to select the ADC reference ...
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MODE REGISTER 2 MR2 (MR20–MR27) (Address (SR4–SR0) = 02H) Figure 18 shows the various operations under the control of Mode Register 2. MR2 BIT DESCRIPTION Analog Input Configuration (MR20–MR23) This control selects the analog input configuration five CVBS ...
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ADV7202 AGC REGISTER 0 AR0 (AR00–AR07) (Address (SR4–SR0) = 04H) Figure 20 shows the various operations under the control of AGC Register 0. AR0 BIT DESCRIPTION AGC Multiplier (AR00–AR07) This register holds the last eight bits of the 12-bit AGC ...
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CLAMP REGISTER 0 CR0 (CR00–CR07) (Address (SR4–SR0) = 06H) Figure 21 shows the various operations under the control of Clamp Register 0. CR0 BIT DESCRIPTION Clamp Level/16 (CR00–CR06) To perform an accurate AGC gain operation necessary to know ...
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ADV7202 CLAMP REGISTER 2 CR2 (CR20–CR27) (Address (SR4–SR0) = 08H) Figure 23 shows the various operations under the control of Clamp Register 2. CR2 BIT DESCRIPTION Fine Clamp 0 Up/Down (CR20) This bit controls the direction of fine clamp number ...
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TIMING REGISTER TR (TR00–TR07) (Address (SR4–SR0) = 0AH) Figure 25 shows the various operations under the control of the Timing Register. TR BIT DESCRIPTION Crystal Oscillator Circuit (TR00) If this bit is set to “0,” the internal oscillator circuit will ...
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ADV7202 AUXILIARY MONITORING REGISTERS AU (AU00–AU07) (Address (SR4–SR0) = 10H) There are eight Auxiliary Monitoring Registers. These registers are read-only; when the device is configured for auxiliary inputs, AU07 AU15 AU23 AU31 they will display a value corresponding to the ...
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AU39 AU47 AU55 AU63 REV. 0 AU38 AU37 AU36 AU35 AU34 AUX REGISTER 4 AU39–AU32 8-BIT [7:0] VALUE CORRESPONDING TO AUX4 INPUT VALUE Figure 31. AUX Register 4 AU46 AU45 AU44 AU43 AU42 AUX REGISTER 5 AU47–AU40 8-BIT [7:0] VALUE ...
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ADV7202 CLAMP CONTROL The clamp control has two modes of operation, if the synchronize clamp control bit CR16 (Bit-6 address 07h) is set, then the clamps that are enabled will be switched on for the programmed time when triggered by ...
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F UNUSED INPUTS SHOULD BE GROUNDED 0.1 F DVDD DVDD 4.7k 4.7 F 6.3V 27MHz CLOCK REV. 0 POWER SUPPLY DECOUPLING FOR EACH POWER SUPPLY GROUP 10 F AVDD DVDD 0 ...
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ADV7202 1.45 1.40 1.35 0.15 SEATING 0.05 PLANE VIEW A ROTATED 90 CCW OUTLINE DIMENSIONS 64-Lead Plastic Quad Flatpack [LQFP] (ST-64B) Dimensions shown in millimeters 0.75 1.60 0.60 MAX 0. SEATING PLANE TOP VIEW (PINS DOWN) 0.20 0.09 ...
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