ADV7202KST Analog Devices Inc, ADV7202KST Datasheet - Page 21

• Manufacturer Part Number: ADV7202KST
• Description: IC CODEC VIDEO 10BIT 64LQFP
• Manufacturer: Analog Devices Inc
• Type: Video Codecr

Specifications of ADV7202KST

• Rohs Status: RoHS non-compliant
• Data Interface: Serial
• Resolution (bits): 12, 10 b
• Number Of Adcs / Dacs: 1 / 4
• Sigma Delta: No
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / Rohs Status: Not Compliant

TIMING REGISTER
TR (TR00–TR07)
(Address (SR4–SR0) = 0AH)
Figure 25 shows the various operations under the control of the
Timing Register.
TR BIT DESCRIPTION
Crystal Oscillator Circuit (TR00)
If this bit is set to “0,” the internal oscillator circuit will be
disabled. Disabling the oscillator circuit is possible when an
external clock module is used, thus saving power.
ADC Bias Currents (TR01)
If this bit is set to “1,” all analog bias currents will be doubled.
VREF ADJUST REGISTER
VR (VR00–VR07)
(Address (SR4–SR0) = 0BH)
Figure 26 shows the various operations under the control of the
VREF Adjust Register.
VR BIT DESCRIPTION
Reserved (VR00)
This register is reserved and “1” must be written to this bit.
Reserved (VR01–VR03)
Zero must be written to these registers.
REV. 0
ZERO MUST BE
WRITTEN TO
THIS BIT
ZERO MUST BE
WRITTEN TO
THIS BIT
TR07
TR07
VR07
VR07
TR06 TR05
0
0
1
1
VR06 VR05
0
0
0
0
1
1
1
1
CLOCK DELAY
ADC REFERENCE VOLTAGE ADJUST
0
1
0
1
TR06
VR06
0
0
1
1
0
0
1
1
0ns
4ns
6ns
8ns
VR04
0
1
0
1
0
1
0
1
TR05
Figure 26. ADC VREF Register
VR05
Figure 25. Timing Register 0
DEFAULT NOMINAL
+14mV
+28mV
+42mV
–14mV
–28mV
–42mV
–56mV
ZERO MUST BE
WRITTEN TO
THIS BIT
TR04
TR04
VR04
TR03
0
1
–21–
DUTY CYCLE
EQUALIZER
INACTIVE
ACTIVE
TR03
Duty Cycle Equalizer (TR03)
When this bit is set to “1,” the clock duty cycle equalizer circuit
is active. This will only have an effect on the ADC operation.
The digital core clock will not be affected.
Clock Delay (TR05–TR06)
Using these two bits, it is possible to insert a delay in the clock
signal to the digital core. These bits control the insertion of
the delay.
Reserved (TR02, TR04, TR07)
Zero must be written to the bits in these registers.
ADC Reference Voltage Adjust (VR04–VR06)
By setting the value of this 3-bit word, it is possible to trim the
ADC internal voltage reference VREFADC.
Reserved (VR07)
Zero must be written to this register.
VR03
ZERO MUST BE
WRITTEN TO
THIS BIT
ZERO MUST BE
WRITTEN TO
THESE BITS
VR03–VR01
TR02
TR02
VR02
TR01
0
1
CURRENTS
ADC BIAS
TR01
NORMAL
DOUBLE
VR01
OSCILLATOR CIRCUIT
TR00
0
1
ONE MUST BE
WRITTEN TO
THIS BIT
CRYSTAL
TR00
VR00
DISABLE
ENABLE
VR00
ADV7202