ADV7202KST Analog Devices Inc, ADV7202KST Datasheet - Page 5

• Manufacturer Part Number: ADV7202KST
• Description: IC CODEC VIDEO 10BIT 64LQFP
• Manufacturer: Analog Devices Inc
• Type: Video Codecr

Specifications of ADV7202KST

• Rohs Status: RoHS non-compliant
• Data Interface: Serial
• Resolution (bits): 12, 10 b
• Number Of Adcs / Dacs: 1 / 4
• Sigma Delta: No
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / Rohs Status: Not Compliant

3.3 V SPECIFICATIONS
Parameter
STATIC PERFORMANCE_DAC
VIDEO ADC
AUX ADC
DIGITAL INPUTS
DIGITAL OUTPUTS
ANALOG OUTPUTS
VOLTAGE REFERENCE
NOTES
1
2
3
Specifications subject to change without notice.
REV. 0
0°C to 70°C.
SHA gain = 1, half range for SHA gain = 2, see Table II.
Output delay measured from 50% of the rising edge of the clock to the 50% point of full-scale transition.
Resolution (Each DAC)
Accuracy (Each DAC)
Integral Nonlinearity
Differential Nonlinearity
Resolution
Accuracy
Integral Nonlinearity
Differential Nonlinearity
Differential Input Voltage Range
SNR
Resolution
Differential Nonlinearity
Integral Nonlinearity
Input Voltage Range
Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, C
Output High Voltage, V
Output Low Voltage, V
Three-State Leakage Current
Output Capacitance
Digital Output Access Time, t
Digital Output Hold Time, t
Output Current
DAC-to-DAC Matching
Output Compliance, V
Output Impedance, R
Output Capacitance, C
Analog Output Delay
DAC Output Skew
Reference Range, V
Reference Range, V
IN
REFADC
REFDAC
3
IN
INL
OUT
INH
OC
OUT
OL
OH
15
14
2
(AVDD/DVDD = 3.3 V
Min
–V
0
2
2.4
0
REFADC
Typ
10
10
± 1
12
12
± 4
± 1
60
55
8
± 0.5
± 0.5
± 1
10
10
10
6
5
4.33
4
50
30
5.5
0.06
1.100
1.235
–0.8/0.1
5%, V
REF
= 1.235 V, R
Max
+V
2 V
0.8
0.4
1.4
–5–
REFADC
REFADC
SET
= 1.2 k , all specifications T
Unit
Bits
Bits
LSB
LSB
Bits
Bits
LSB
LSB
dB
dB
Bits
LSB
LSB
V
V
V
µA
pF
V
V
µA
pF
ns
ns
mA
%
V
kΩ
pF
ns
ns
V
V
(Including 2 Bits for Gain Ranging)
Test Conditions
10-Bit Operation
10-Bit Operation
2.2 V Ref.
12 Bit
12 Bit
See Table II
27 MHz Clock, f
54 MHz Clock
I
I
See Figure 13
R
DAC 0, 1, and 2
I
SOURCE
SINK
OUT
SET
= 0 mA
= 1.2 kΩ, R
= 1.6 mA
= 400 µA
MIN
to T
MAX
1
IN
L
, unless otherwise noted.)
= 300 Ω
= 100 kHz
ADV7202