ADM6996LX-AA-T-1 Infineon Technologies, ADM6996LX-AA-T-1 Datasheet
ADM6996LX-AA-T-1
Specifications of ADM6996LX-AA-T-1
SP000076442
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ADM6996LX-AA-T-1 Summary of contents
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... An Infineon Technologies Company ADM6996L 6 port 10/100 Mb/s Single Chip Ethernet Switch Controller Infineon-ADMtek Co Ltd Information in this document is provided in connection with Infineon-ADMtek Co Ltd products. Infineon- ADMtek Co Ltd may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” ...
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Infineon-ADMtek Co. Ltd. About this Manual General Release Intended Audience Infineon-ADMtek Co Ltd’s Customers Structure This Data sheet contains 6 chapters Chapter 1 Product Overview Chapter 2 Interface Description Chapter 3 Function Description Chapter 4. Register Description Chapter 5. Electrical ...
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Infineon-ADMtek Co. Ltd. Table of Contents Chapter 1 Product Overview ........................................................................................ 1-1 1.1 Overview.......................................................................................................... 1-1 1.2 Features ............................................................................................................ 1-2 1.3 Applications ..................................................................................................... 1-2 1.4 Block Diagram ................................................................................................. 1-3 1.5 Abbreviations................................................................................................... 1-3 1.6 Conventions ..................................................................................................... 1-5 1.6.1 Data Lengths............................................................................................ 1-5 1.6.2 ...
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Infineon-ADMtek Co. Ltd. 3.8 Jabber Function................................................................................................ 3-7 3.9 Link Test Function........................................................................................... 3-7 3.10 Automatic Link Polarity Detection.............................................................. 3-8 3.11 Clock Synthesizer ........................................................................................ 3-8 3.12 Auto Negotiation.......................................................................................... 3-8 3.13 Memory Block ............................................................................................. 3-8 3.14 Switch Functional Description..................................................................... 3-9 3.15 Basic Operation............................................................................................ ...
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Infineon-ADMtek Co. Ltd. 4.3.21 Reserved Register, offset: 0x2dh.............................................................. 4-2 4.3.22 Reserved Register, offset: 0x2eh .............................................................. 4-2 4.3.23 PHY Restart, offset: 0x2fh........................................................................ 4-2 4.3.24 Miscellaneous Configuration Register, offset: 0x30h.............................. 4-2 4.3.25 Bandwidth Control Register0~3, offset: 0x31h........................................ 4-3 4.3.26 Bandwidth Control Register ...
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ADM6996L Chapter 1 Product Overview 1.1 Overview The ADM6996L is a high performance, low cost, highly integration (Controller, PHY and Memory) five-port 10/100 Mbps TX/FX plus one 10/100 MAC port Ethernet switch controller with all ports supporting 10/100 Mbps Full/Half ...
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ADM6996L 1.2 Features Supports five 10M/100M auto-detect Half/Full duplex switch ports with TX/FX • interfaces and one MII/GPSI port. Supports 2048 MAC addresses table. • Supports four queue for QoS • Supports priority features by Port-Based, 802.1p VLAN & IP ...
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ADM6996L 1.4 Block Diagram 10/100M MAC Twisted Pair Interface RXP4 RXN4 TXP4 TXN4 1.5 Abbreviations BER CFI COL CRC CRS EDI EDO EECS Infineon-ADMtek Co. Ltd. Embedded Memory Switching Fabric ... 10/100M 10/100M MAC PORT0 PORT1 ...
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ADM6996L EESK ESD FEFI FET FLP GND GPSI IPG LFSR MAC MDIX MII NRZI NRZ PCS PHY PLL PMA PMD QoS QFP RST RXCLK RXD RXDV RXER RXN RXP SA SOHO SSD SQE TOS TP TTL TXCLK TXD TXEN TXN ...
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ADM6996L 1.6 Conventions 1.6.1 Data Lengths qword dword word byte nibble 1.6.2 Pin Types Pin Type I O I/O OD SCHE PD PU 1.6.2 Register Types Register Type Infineon-ADMtek Co. Ltd. 64-bits 32-bits 16-bits 8 bits 4 ...
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ADM6996L Chapter 2 Interface Description 2.1 Pin Diagram 103 DUPCOL4 104 GNDO 105 VCC3O 106 DUPCOL3 107 DUPCOL2 (BPEN) 108 DUPCOL1 (PHYAS1) 109 DUPCOL0 (RECANEN) 110 VCCIK 111 GNDIK 112 RC 113 XI 114 XO 115 VCCPLL 116 GNDPLL 117 ...
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ADM6996L 2.2 Pin Description by Function ADM6996L pins are categorized into one of the following groups: Section 2.2.1 Twisted Pair Interface Section 2.2.2 6th Port (MII) Interfaces Section 2.2.3 LED Interface Section 2.2.4 EEPROM/Management Interface Section 2.2.5 Power/Ground, 48 pins ...
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ADM6996L Pin Name P4FX XEN Setting PHYAS0 RXD[0] RXD[3:1] 102, 101, RXDV RXER COL CRS RXCLK TXCLK DHALFP5 LNKFP5 SPDTNP5 Infineon-ADMtek Co. Ltd. Pin# Type Descriptions 8mA Synchronous to the rising edge of TXCLK. These pins act PD as MII ...
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ADM6996L 2.2.3 LED Interface Pin Name LNKACT[4:0] 92, 95, 96, 97, 98 DUPCOL[4:3] 103, 106 DUPCOL2 Setting BPEN DUPCOL1 Setting PHYAS1 DUPCOL0 Setting ANEN LDSPD[4:0] 58, 55, 54, 51, 50 Infineon-ADMtek Co. Ltd. Pin# Type Descriptions O, LINK/Activity LED[4:0]. Active ...
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ADM6996L 2.2.4 EEPROM/Management Interface Pin Name EDO EECS EECK Setting XOVEN EDI Setting LEDMODE 2.2.5 Power/Ground, 48 pins Pin Name GNDA 3, 10, 16, 23, 29, 36, 42, 125 VCCA2 6, 7, 19, 20, 32, 33, 45, 122 VCCAD 13, ...
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ADM6996L 2.2.6 MISC Pin Name CKO25M Control RTX VREF CFG0 TEST 4,5, 14, 15,17, 18, 27,28, Infineon-ADMtek Co. Ltd. Pin# Type Descriptions 85 O, 25M Clock Output. 8mA 117 O FET Control Signal. The ...
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ADM6996L Chapter 3 Function Description 3.1 Functional Descriptions The ADM6996L integrates five 100Base-X physical sub-layer (PHY), 100Base-TX physical medium dependent (PMD) transceivers, five complete 10Base-T modules, 6 port 10/100 switch controller and one 10/100 MII/GPSI MAC and memory into a ...
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ADM6996L 3.4 100Base-X Receiver The 100Base-X receiver consists of functional blocks required to recover and condition the 125Mbits/s receive data stream. receiving state machine diagram as given in ANSI/IEEE Standard 802.3u, Clause 24. The 125Mbits/s receive data stream may originate ...
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ADM6996L 3.4.4 Data De-scrambling The de-scrambler acquires synchronization with the data stream by recognizing idle bursts more bits and locking its deciphering Linear Feedback Shift Register (LFSR) to the state of the scrambling LFSR. Upon achieving synchronization, ...
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ADM6996L 3.4.8 Receive Errors The RXER signal is used to communicate receiver error conditions. While the receiver state of holding RXDV asserted, the RXER will be asserted for each code word that does not map to a ...
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ADM6996L 3.4.12 Far-End Fault Auto negotiation provides a mechanism for transferring information from the Local Station to the link Partner that a remote fault has occurred for 100Base-TX. As auto negotiation is not currently specified for operation over fiber, the ...
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ADM6996L functions, as defined in the standard. Figure 3 provides an overview for the 10Base-T module. The ADM6996L 10Base-T module is comprised of the following functional blocks: • Manchester encoder and decoder • Collision detector • Link test function • ...
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ADM6996L and timing measurements (as specified in the IEEE 802.3 10Base-T standard) to determine the validity of data on the twisted-pair inputs. The signal at the start of the packet is checked by the analog squelch circuit and any pulses ...
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ADM6996L 3.10 Automatic Link Polarity Detection ADM6996L’s 10Base-T transceiver module incorporates an “automatic link polarity detection circuit”. The inverted polarity is determined when seven consecutive link pulses of inverted polarity or three consecutive packets are received with inverted end-of-packet pulses. ...
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ADM6996L 3.14 Switch Functional Description The ADM6996L uses a “store & forward” switching approach for the following reason: Store & forward switches allow switching between different speed media (e.g. 10BaseX and 100BaseX). Such switches require the large elastic buffer especially ...
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ADM6996L 3.15.2 Address Recognition and Packet Forwarding The ADM6996L forwards the incoming packets between bridged ports according to the Destination Address (DA) as below. All the packet forwarding will check VLAN first. Forwarding port must same VLAN with source port. ...
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ADM6996L 3.15.6 Illegal Frames The ADM6996L will discard all illegal frames such as runt packet (less than 64 bytes), oversize packet (greater than 1518 or 1522 bytes) and bad CRC. Dribbling packing with good CRC value will accept by ADM6996L. ...
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ADM6996L Switch connect other device such as another Switch must by two way. First one is Cross Over TP cable. Second way is use extra RJ45 which crossover internal TX+- and RX+- signal. By second way customer can use one ...
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ADM6996L as receiving port then this packet will be dropped. Example2: Port receives Untag packet and send to Tag port. ADM6996L will check the port user define fours bits of VLAN ID first then check VLAN group resister. If destination ...
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ADM6996L ADM6996L LED is active Low signal. Dupcol0 & Dupcol1 will check external signal at Reset time. If external signal add pull high then LED will active Low. If external signal add pull down resister then LED will drive high. ...
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ADM6996L Chapter 4 Register Description 4.1 EEPROM Content EEPROM provides ADM6996L many options setting such as: • Port Configuration: Speed, Duplex, Flow Control Capability and Tag/ Untag. • VLAN & TOS Priority Mapping • Broadcast Storming rate and Trunk. • ...
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ADM6996L Register 0x1ah VLAN 7 outbound Port Map 0x1bh VLAN 8 outbound Port Map 0x1ch VLAN 9 outbound Port Map 0x1dh VLAN 10 outbound Port Map 0x1eh VLAN 11 outbound Port Map 0x1fh VLAN 12 outbound Port Map 0x20h VLAN ...
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ADM6996L 4.3.2 Configuration Registers, offset: 0x01h ~ 0x09h Bits Type Description 0 R/W 802.3x Flow control command ability. 1: enable. 0: disable. 1 R/W Auto negotiation Enable. 1: enable, 0: disable. 2 R/W Speed. 1: 100M, 0: 10M. 3 R/W ...
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ADM6996L 4.3.4 Configuration Register, offset: 0x0bh Bits Type Description 5:0 RO Reserved 6 R/W Enable IPG leveling. 1/92 bit. 0/96 bit. Note: When this bit is enable ADM6996L will transmit packet out at 92 bit IPG to clean buffer. If ...
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ADM6996L Bits Type Description 13:12 R/W Mapped priority of tag value (TOS) 6. 15:14 R/W Mapped priority of tag value (TOS) 7. Note: Value are for priority queue Q3~Q0 respectively. The Weight ratio ...
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ADM6996L 4.3.10 TOS IP Packet ADM6996L check byte 12 &13 if this value is 0800h then ADM6996L knows this is a TOP priority packet. Type 0800 Byte 12~13 IP header define Byte 14 Bit[7:0]: IP protocol version number & header ...
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ADM6996L Note (Continued): - per port rising threshold 00 All Disable 100TX Not All Disable 100TX - per port falling threshold 00 All Disable 100TX Not All Disable 100TX Bit 2: Broadcast Storming Enable. 0/Disable. 1/Enable. Bit 4: CRC check ...
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ADM6996L Below is Router old architecture. The disadvantages of this are: 1. WAN port only support 10M Half-Duplex and non-MDIX function. 2. Need extra 10M NIC cost. 3. ISA bus will become bottleneck of whole system. CPU with one MII ...
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ADM6996L Switch. One is original Card and another one is CPU. This will make Switch learning table trouble. ADM6996L provide MAC Clone function that allow two same MAC address with different VLAN ID0 on learning table. This will solve Lock ...
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ADM6996L ADM6996L will check VLAN mapping setting first then check learning table. User does not worry LAN/WAN traffic mix up. Bit 10: Half Duplex Back Pressure enable. 1/enable, 0/disable. 4.3.13 Miscellaneous Configuration register, offset: 0x12h Bits Type Description 0 R/W ...
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ADM6996L 4.3.16 Port0, 1 PVID bit Configuration Register, offset: 0x28h Bits Type Description 7:0 R/W Port0 PVID bit 11~4. These 8 bits combine with register 0x01h Bit [13~10] as full 12 bit VID. 15:8 RO Reserved 4.3.17 ...
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ADM6996L Bits Type Description 14 R/W Control reserved MAC (0180C2000001) 1: Forward, 0: Discard. 15 R/W Control reserved MAC (0180C2000000) 1: Forward, 0: Discard. Note: Bit[10:8]: VLAN Tag shift register. ADM6996L will select 4 bit from total 12 bit VID ...
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ADM6996L Bits Type Description 11 R/W Reserved 12 R/W Port 4 LED Mode. 1:Link/Act/Speed 0:LinkAct/DupCol/Speed 15:13 R/W Reserved 4.3.25 Bandwidth Control Register0~3, offset: 0x31h Bits Type Description 2:0 R/W Port 0 Meter Threshold Control. Reference table below. 3 R/W Receive ...
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ADM6996L 4.3.27 Bandwidth Control Enable Register, offset: 0x33h Bits Type Description 0 R/W Bandwidth Control Enable for Port Port 0 enables the bandwidth control Port 0 disables the bandwidth control. 1 R/W Reserved 2 R/W ...
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ADM6996L ADM6996L serial chips will latch hardware-reset value as recommend value. It includes EEPROM interface: EECS: Internal Pull down 40K resister. EESK: TP port Auto-MDIX select. Internal pull down 40K resister as non Auto-MDIX mode. EDI: Dual Color Select. Internal ...
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ADM6996L 4.5 Serial Register Map Register 0x00h 0x01h 0x02h 0x03h 0x04h 0x05h 0x06h 0x07h 0x08h 0x09h 0x0ah 0x0bh 0x0ch 0x0dh 0x0eh 0x0fh 0x10h 0x11h 0x12h 0x13h 0x14h 0x15h 0x16h 0x17h 0x18h 0x19h 0x1ah 0x1bh 0x1ch 0x1dh 0x1eh 0x1fh 0x20h 0x21h ...
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ADM6996L Register 0x2ah 0x2bh 0x2ch 0x2dh 0x2eh 0x2fh 0x30h 0x31h 0x32h 0x33h 0x34h 0x35h 0x36h 0x37h 0x38h 0x39h 0x3ah 0x3bh 0x3ch 4.6 Serial Register Description 4.6.1 Chip Identifier Register, offset: 0x00h Bits Type Description 3:0 RO 0000 (Version number) 31:4 ...
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ADM6996L Bits Type Description 5 RO Reserved 6 RO Reserved 7 RO Reserved 8 RO Port 1 Linkup Status: 1: Link is established. 0: Link is not established Port 1 Speed Status: 1: 100Mb Mb/s 10 ...
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ADM6996L Bits Type Description 1: 802.3X on for full duplex or back pressure on for half duplex. 0: Flow Control Disable 28 RO Port 4 Linkup Status: 1: Link is established. 0: Link is not established Port 4 ...
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ADM6996L Bits Type Description 7:6 RO Port 1 Cable Broken Length 8 RO Port 1 Cable Broken 10:9 RO Reserved 11 RO Reserved 3:12 RO Port 2 Cable Broken Length 14 RO Port 2 Cable Broken 16:15 RO Reserved 17 ...
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ADM6996L Bits Type Description 3 RO Reserved 4 RO Overflow of Port 2 Transmit Packet Count 5 RO Reserved 6 RO Overflow of Port 3 Transmit Packet Count 7 RO Overflow of Port 4 Transmit Packet Count 8 RO Overflow ...
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ADM6996L 4.7 Serial Interface Timing ADM6996L serial chip internal counter or EEPROM access timing. EESK: Similar as MDC signal. EDI: Similar as MDIO. ECS: Must keep low. EECK EEDI (STA) EEDI (AT8999 Opcode Table ...
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ADM6996L Preamble: At least 32 continuous “1”. Start: 01(2 bits) Opcode bits, Reset command) Device Address: Chip physical address as PHYAS[1:0]. Reset_type: Reset counter by port number or by counter index. 1: Clear dedicate port’s all counters. 0: ...
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ADM6996L Chapter 5 Electrical Specification 5.1 TX/FX Interface 5.1.1 TP Interface TXP TXN ADM6995 RXP RXN Transformer requirement: . TX/RX rate 1:1 . TX/RX central tap connect together to VCCA2. User can change TX/RX pin for easy layout but do ...
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ADM6996L 5.2 DC Characteristics 5.2.1 Absolute Maximum Rating Symbol Parameter V Power Supply CC Vcca2 TX line driver Vccpll PLL voltage Vccik Digital core voltage V Input Voltage IN Vout Output Voltage TSTG Storage Temperature PD Power Dissipation ESD ESD ...
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ADM6996L 5.3 AC Characteristics 5.3.1 Power On Reset RST* All Configuration Pins Symbol Parameter TRST RST Low Period TCONF Start of Idle Pulse Width 5.3.2 EEPROM Interface Timing 0us EECS EESK tEWDD EEDO EEDI Symbol Parameter TESK EESK Period TESKL ...
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ADM6996L 5.3.3 10Base-TX MII Input Timing 0ns MII_RXCLK MII_RXDV MII_RXD MII_CRS Symbol Parameter tCK MII_RXCLK Period tCKL MII_RXCLK Low Period tCKH MII_RXCLK High Period tRXS MII_CRS, MII_RXDV and MII_RXD to MII_RXCLK rising setup tRXH MII_CRS, MII_RXDV and MII_RXD to MII_RXCLK ...
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ADM6996L 5.3.5 100Base-TX MII Input Timing 0ns MII_RXCLK MII_RXDV MII_RXD MII_CRS Symbol Parameter tCK MII_RXCLK Period tCKL MII_RXCLK Low Period tCKH MII_RXCLK High Period tRXS MII_CRS, MII_RXDV and MII_RXD to MII_RXCLK rising setup tRXH MII_CRS, MII_RXDV and MII_RXD to MII_RXCLK ...
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ADM6996L Symbol Parameter tCKH MII_TXCLK High Period tTXOD MII_TXD, MII_TXEN to MII_TXCLK Rising Output Delay 5.3.7 GPSI(7-wire) Input Timing 0ns GPSI_RXCLK GPSI_RXD GPSI_CRS/COL Symbol Parameter TCK GPSI_RXCLK Period TCKL GPSI_RXCLK Low Period TCKH GPSI_RXCLK High Period TTXS GPSI_RXD, GPSI_CRS/COL to ...
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ADM6996L Symbol Parameter TCK GPSI_TXCLK Period TCKL GPSI_TXCLK Low Period TCKH GPSI_TXCLK High Period TOD GPSI_TXCLK Rising to GPSI_TXEN/GPSI_TXD Output Delay Infineon-ADMtek Co. Ltd. Conditions Min Typical 100 Electrical Specification Max Units ...
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ADM6996L Chapter 6 Packaging 6.1 128 Pin PQFP Outside Dimension Infineon-ADMtek Co. Ltd. 17.2 +/- 0.2 mm 14.0 +/- 0.1 mm 12.5 mm 0.5 mm Appendix 6-1 ...