ISP1761BEUM ST-Ericsson Inc, ISP1761BEUM Datasheet - Page 123

• Manufacturer Part Number: ISP1761BEUM
• Description: IC USB OTG CONTROLLER HS 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1761BEUM

• Controller Type: USB Peripheral Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 568-1888-2; ISP1761BE,518; ISP1761BE-T

NXP Semiconductors
Table 137. DMA Endpoint register (address 0258h) bit allocation
[1]
Table 139. DMA Burst Counter register (address 0264h) bit allocation
[1]
ISP1761_5
Product data sheet
Bit
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
The reserved bits should always be written with the reset value.
The reserved bits should always be written with the reset value.
10.7.8 DMA Burst Counter register
R/W
R/W
R/W
15
7
0
0
0
0
7
0
0
Table 138. DMA Endpoint register (address 0258h) bit description
The DMA Endpoint register must not reference the endpoint that is indexed by the
Endpoint Index register (022Ch) at any time. Doing so will result in data corruption.
Therefore, if the DMA Endpoint register is unused, point it to an unused endpoint. If the
DMA Endpoint register, however, is pointed to an active endpoint, the firmware must not
reference the same endpoint on the Endpoint Index register.
The bit allocation of the register is given in
Bit
7 to 4
3 to 1
0
reserved
R/W
R/W
R/W
14
6
0
0
0
0
6
0
0
[1]
Symbol
-
EPIDX[2:0]
DMADIR
R/W
R/W
R/W
13
5
0
0
0
0
5
0
0
Rev. 05 — 13 March 2008
Description
reserved
Selects the indicated endpoint for DMA access
DMA Direction:
0 — Selects the RX/OUT FIFO for DMA write transfers
1 — Selects the TX/IN FIFO for DMA read transfers
BURSTCOUNTER[7:0]
R/W
R/W
R/W
12
4
0
0
0
0
4
0
0
…continued
Table
R/W
R/W
R/W
11
3
0
0
0
0
3
0
0
BURSTCOUNTER[12:8]
139.
R/W
R/W
R/W
10
2
0
0
0
0
2
1
1
Hi-Speed USB OTG controller
R/W
R/W
R/W
1
0
0
9
0
0
1
0
0
© NXP B.V. 2008. All rights reserved.
ISP1761
122 of 163
R/W
R/W
R/W
0
0
0
8
0
0
0
0
0