ISP1761BEUM ST-Ericsson Inc, ISP1761BEUM Datasheet - Page 43

• Manufacturer Part Number: ISP1761BEUM
• Description: IC USB OTG CONTROLLER HS 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1761BEUM

• Controller Type: USB Peripheral Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 568-1888-2; ISP1761BE,518; ISP1761BE-T

NXP Semiconductors
Table 29.
Table 30.
Table 31.
Table 32.
ISP1761_5
Product data sheet
Bit
31 to 0
Bit
31 to 0
Bit
31 to 0 ATL_PTD_DONE_
Bit
31 to 0
Symbol
MAP[31:0]
Symbol
INT_PTD_SKIP_
MAP[31:0]
Symbol
INT_PTD_LAST_
PTD[31:0]
Symbol
ATL_PTD_SKIP_
MAP[31:0]
INT PTD Skip Map register (address 0144h) bit description
INT PTD Last PTD register (address 0148h) bit description
ATL PTD Done Map register (address 0150h) bit description
ATL PTD Skip Map register (address 0154h) bit description
8.2.12 INT PTD Last PTD register
8.2.13 ATL PTD Done Map register
8.2.14 ATL PTD Skip Map register
When a bit in the PTD Skip map is set to logic 1 that PTD will be skipped although its V bit
may be set. The information in that PTD is not processed. For example, NextPTDPointer
will not affect the order of processing of PTDs. The Skip bit should not normally be set on
the position indicated by NextPTDPointer.
The bit description of the register is given in
Once the LastPTD bit corresponding to a PTD is set, this will be the last PTD processed
(checking V = 1) in that PTD category. Subsequently, the process will restart with the first
PTD of that group. This is useful to reduce the time in which all the PTDs, the respective
memory space, would be checked, especially if only a few PTDs are defined. The
LastPTD bit must normally be set to a higher position than any other position indicated by
the NextPTDPointer from an active PTD.
Table 31
This register represents a direct map of the done status of the 32 PTDs. The bit
corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is
completed. Reading the Done Map register will clear all the bits that are set to logic 1, and
the next reading will reflect the updated status of new executed PTDs.
The bit description of the register is given in
Access
R/W
Access
R
Access
R/W
Access Value
R/W
shows the bit description of the ATL PTD Done Map register.
Value
0000 0000h
Value
FFFF FFFFh INT PTD Skip Map: Skip map for each of the 32 PTDs for the INT
Value
0000 0000h INT PTD Last PTD: Last PTD of the 32 PTDs.
FFFF FFFFh
Rev. 05 — 13 March 2008
Description
1h — One PTD in INT
2h — Two PTDs in INT
3h — Three PTDs in INT
Description
ATL PTD Done Map: Done map for each of the 32 PTDs for the ATL
transfer
Description
transfer
Description
ATL PTD Skip Map: Skip map for each of the 32 PTDs for the ATL
transfer
Table
Table
30.
32.
Hi-Speed USB OTG controller
© NXP B.V. 2008. All rights reserved.
ISP1761
42 of 163