ISP1761BEUM ST-Ericsson Inc, ISP1761BEUM Datasheet - Page 126

• Manufacturer Part Number: ISP1761BEUM
• Description: IC USB OTG CONTROLLER HS 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1761BEUM

• Controller Type: USB Peripheral Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 568-1888-2; ISP1761BE,518; ISP1761BE-T

NXP Semiconductors
Table 143. DcChipID - Device Controller Chip Identifier register (address 0270h) bit description
Table 144. Frame Number register (address 0274h) bit allocation
ISP1761_5
Product data sheet
Bit
31 to 0
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Symbol
CHIPID[31:0]
10.8.2 DcChipID register
10.8.3 Frame Number register
10.8.4 DcScratch register
15
R
R
0
0
7
0
0
reserved
Table 142. DcInterrupt - Device Controller Interrupt register (address 0218h) bit
This read-only register contains the chip identification and hardware version numbers.
The firmware must check this information to determine functions and features supported.
The register contains 3 bytes, and the bit allocation is shown in
This read-only register contains the frame number of the last successfully received
Start-Of-Frame (SOF). The register contains 2 bytes, and the bit allocation is given in
Table
Table 145. Frame Number register (address 0274h) bit description
This 16-bit register can be used by the firmware to save and restore information. For
example, the device status before it enters the suspend state; see
Bit
2
1
0
Bit
15 to 14
13 to 11
10 to 0
Access
R
144.
14
R
R
0
0
6
0
0
description
Symbol
PSOF
SOF
BRESET
Symbol
-
MICROSOF[2:0]
SOFR[10:0]
Value
0015 8210h Chip ID: This registers represents the hardware version number
13
R
R
0
0
5
0
0
…continued
Rev. 05 — 13 March 2008
Description
Pseudo SOF interrupt: Logic 1 indicates that a pseudo SOF or SOF
was received. Pseudo SOF is an internally generated clock signal
(full-speed: 1 ms period, high-speed: 125 s period) that is not
synchronized to the USB bus SOF or SOF.
SOF interrupt: Logic 1 indicates that a SOF or SOF was received.
Bus Reset: Logic 1 indicates that a USB bus reset was detected.
Description
(0015h) and the chip ID (8210h) for the peripheral controller.
MICROSOF[2:0]
Description
reserved
microframe number
frame number
12
R
R
0
0
4
0
0
SOFR[7:0]
11
R
R
0
0
3
0
0
10
Hi-Speed USB OTG controller
R
R
0
0
2
0
0
Table
SOFR[10:8]
Table
143.
R
R
9
0
0
1
0
0
© NXP B.V. 2008. All rights reserved.
ISP1761
146.
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R
R
8
0
0
0
0
0