LAN9211-ABZJ SMSC, LAN9211-ABZJ Datasheet - Page 35

• Manufacturer Part Number: LAN9211-ABZJ
• Description: IC ETHERNET CTLR SGL CHIP 56-QFN
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN9211-ABZJ

• Controller Type: Ethernet Controller
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-QFN
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: IEEE 802.3 or IEEE 802.3u
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 5 V
• Supply Voltage (min): 3.3 V
• Supply Current (max): 86 mA
• Maximum Operating Temperature: + 70 C
• Ethernet Connection Type: 100BASE-TX or 10BASE-T
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• No. Of Ports: 2
• Ethernet Type: IEEE 802.3 / 802.3u
• Interface Type: HBI
• Supply Current: 86mA
• Supply Voltage Range: 2.97V To 3.63V
• Operating Temperature Range: 0°C To +70°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1049-6

High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support
Datasheet
SMSC LAN9211
AND/OR (FSELEND = 1 for Data FIFO direct access when FIFO_SEL=1)
AND/OR (FSELEND = 1 for Data FIFO direct access when FIFO_SEL=1)
31
(FPORTEND = 1 for Data FIFO port access on addresses 00h-3Ch)
31
(FPORTEND = 1 for Data FIFO port access on addresses 00h-3Ch)
MSB
MSB
A[1] = 1
A[1] = 0
A[1] = 1
A[1] = 0
3
3
24
24
23
15
23
15
INTERNAL FIFO ORDER
INTERNAL FIFO ORDER
HOST DATA BUS
HOST DATA BUS
BIG ENDIAN
BIG ENDIAN
2
0
2
2
2
0
16
16
8
8
7
15
7
15
1
1
3
1
3
1
Figure 3.3 FIFO Access Byte Ordering
8
8
WORD_SWAP != FFFF_FFFFh
0
0
WORD_SWAP = FFFF_FFFFh
7
7
LSB
LSB
0
0
DATASHEET
0
0
35
AND/OR (FSELEND = 0 for Data FIFO direct access when FIFO_SEL=1)
AND/OR (FSELEND = 0 for Data FIFO direct access when FIFO_SEL=1)
31
31
(FPORTEND = 0 for Data FIFO port access on addresses 00h-3Ch)
(FPORTEND = 0 for Data FIFO port access on addresses 00h-3Ch)
MSB
MSB
A[1] = 1
A[1] = 0
A[1] = 0
A[1] = 1
3
3
24
24
23
15
15
23
INTERNAL FIFO ORDER
INTERNAL FIFO ORDER
LITTLE ENDIAN
LITTLE ENDIAN
HOST DATA BUS
HOST DATA BUS
3
1
2
2
1
3
16
16
8
8
7
15
7
15
2
0
1
0
2
1
8
8
Revision 2.7 (03-15-10)
0
0
7
7
LSB
LSB
0
0
0
0