LAN9211-ABZJ SMSC, LAN9211-ABZJ Datasheet - Page 41

• Manufacturer Part Number: LAN9211-ABZJ
• Description: IC ETHERNET CTLR SGL CHIP 56-QFN
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN9211-ABZJ

• Controller Type: Ethernet Controller
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-QFN
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: IEEE 802.3 or IEEE 802.3u
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 5 V
• Supply Voltage (min): 3.3 V
• Supply Current (max): 86 mA
• Maximum Operating Temperature: + 70 C
• Ethernet Connection Type: 100BASE-TX or 10BASE-T
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• No. Of Ports: 2
• Ethernet Type: IEEE 802.3 / 802.3u
• Interface Type: HBI
• Supply Current: 86mA
• Supply Voltage Range: 2.97V To 3.63V
• Operating Temperature Range: 0°C To +70°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1049-6

High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support
Datasheet
SMSC LAN9211
EEDIO (OUTPUT)
EEDIO (OUTPUT)
EEDIO (INPUT)
EEDIO (INPUT)
EEDIO (OUTPUT)
EEDIO (INPUT)
EECLK
EECLK
EECS
EECS
READ (Read Location): This command will cause a read of the EEPROM location pointed to by EPC
Address (EPC_ADDR). The result of the read is available in the E2P_DATA register.
WRITE (Write Location): If erase/write operations are enabled in the EEPROM, this command will
cause the contents of the E2P_DATA register to be written to the EEPROM location selected by the
EPC Address field (EPC_ADDR). The EPC_TO bit is set if the EEPROM does not respond within
30ms.
WRAL (Write All): If erase/write operations are enabled in the EEPROM, this command will cause the
contents of the E2P_DATA register to be written to every EEPROM memory location. The EPC_TO bit
is set if the EEPROM does not respond within 30ms.
Table 3.9, "Required EECLK
each EEPROM operation.
EECLK
EECS
1
1
0
0
1
0
Figure 3.10 EEPROM WRITE Cycle
1
Figure 3.11 EEPROM WRAL Cycle
Figure 3.9 EEPROM READ Cycle
1
0
Cycles", shown below, shows the number of EECLK cycles required for
A6
1
0
DATASHEET
A6
41
A0
D7
D7
A0
D7
D0
D0
t
t
CSL
CSL
D0
Revision 2.7 (03-15-10)
t
CSL