SC18IS601IBS,151 NXP Semiconductors, SC18IS601IBS,151 Datasheet - Page 12

• Manufacturer Part Number: SC18IS601IBS,151
• Description: IC SPI TO I2C BUS 24-HVQFN
• Manufacturer: NXP Semiconductors

Specifications of SC18IS601IBS,151

• Package / Case: 24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
• Controller Type: I²C Bus Controller
• Interface: SPI
• Voltage - Supply: 2.4 V ~ 3.6 V
• Current - Supply: 11mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Maximum Operating Frequency: 12 MHz
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.4 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-3511 - DEMO BOARD SPI TO I2C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4710; 935286979151; SC18IS601IBS-S

NXP Semiconductors
SC18IS600_601_5
Product data sheet
6.3 External clock input (SC18IS601)
6.4 I
6.5 Serial Peripheral Interface (SPI)
In this device, the processor clock is derived from an external source driving the CLKIN
pin. The clock rate may be from 0 Hz up to 18 MHz.
I
to the bus, and it has the following features:
A typical I
provides a byte-oriented I
(Refer to UM10204, “I
The host communicates with the SC18IS600/601 via the SPI interface. The
SC18IS600/601 operates in Slave mode up to 3 Mbit/s.
The SPI interface has four pins: SCLK, MOSI, MISO, and CS.
Typical connections are shown in
2
2
Fig 11. I
C-bus uses two wires (SDA and SCL) to transfer information between devices connected
•
•
•
•
•
•
•
•
C-bus serial interface
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
The I
SCLK, MOSI and MISO are typically tied together between two or more SPI devices.
Data flows from the master to the SC18IS600/601 on the MOSI (Master Out Slave In)
pin and flows from SC18IS600/601 to the master on the MISO (Master In Slave Out)
pin. The SCLK signal is an input to the SC18IS600/601.
CS is the slave select pin. In a typical configuration, an SPI master selects one SPI
device as the current slave. An SPI slave device uses its CS pin to determine whether
it is selected. The CS pin may be tied LOW if it is the only device on the bus.
2
2
2
C-bus may be used for test and diagnostic purposes.
C-bus configuration is shown in
C-bus configuration
I
2
C-bus
2
C-bus specification and user manual” .)
Rev. 05 — 28 July 2008
SC18IS600/601
2
C-bus interface that supports data transfers up to 400 kHz.
V
DD
Figure
R PU
12.
Figure
I
DEVICE
2
C-BUS
R PU
11. The SC18IS600/601 device
SC18IS600/601
I
DEVICE
2
C-BUS
SPI to I
002aab716
SDA
SCL
© NXP B.V. 2008. All rights reserved.
2
C-bus interface
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