DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 107

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DS31256 256-Channel, High-Throughput HDLC Controller
Priority Packets
The host has the option to change the order in which packets are transmitted by the DMA. If the host sets
the priority packet (PRI) bit in the pending-queue descriptor to 1, the transmit DMA knows that this
packet is a priority packet and should be transmitted ahead of all standard packets. The rules for packet
transmission are as follows:
1) Priority packets are transmitted as soon as the current standard packet (not packet chain) finishes
transmission.
2) All priority packets are transmitted before any more standard packets are transmitted.
3) Priority packets are ordered on a first come, first served basis.
Figure 9-13
shows an example of a set of priority packets interrupting a set of standard packets. In the
example, the first priority packet chain (shown in column 2) was read by the transmit DMA from the
pending queue while it was transmitting standard packet #1. It waited until standard packet #1 was
complete and then began sending the priority packets. While column 2 was being sent, the priority
packet chains of columns 3 and 4 arrived in the pending queue, so the transmit DMA linked column four
to column three and then waited until all of the priority packets were transmitted before returning to the
standard packet chain in column 1. Note that the packet chain in column 1 was interrupted to transmit the
priority packets. In other words, the transmit DMA did not wait for the complete packet to finish
transmitting, only the current packet.
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