DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 86

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

On an HDLC-channel basis in the receive DMA configuration RAM, the host instructs the DMA how to
use the large and small buffers for the incoming packet data on that particular HDLC channel. The host
has three options: (1) only use large buffers, (2) only use small buffers, or (3) first fill a small buffer,
then, if the incoming packet requires more buffer space, use one or more large buffers for the remainder
of the packet. The host selects the option through the size field in the receive configuration RAM
(Section 9.2.5). Large buffers are best used for data-intensive, time-insensitive packets like graphics
files, whereas small buffers are best used for time-sensitive information like real-time voice.
Table 9-B. Receive DMA Main Operational Areas
The done-queue descriptors contain information that the DMA wishes to pass to the host. Through the
done-queue descriptors, the DMA informs the host about the incoming packet data and where to find the
packet descriptors that it has written into main memory. Each completed descriptor contains the starting
address of the data buffer where the packet data is stored.
If enabled, the DMA can burst read the free-queue descriptors and burst write the done-queue
descriptors. This helps minimize PCI bus accesses, freeing the PCI bus up to do more time critical
functions. See Sections
Receive DMA Actions
A typical scenario for the receive DMA is as follows:
1) The receive DMA gets a request from the receive FIFO that it has packet data that needs to be sent to
2) The receive DMA determines whether the incoming packet data should be stored in a large buffer or
3) The receive DMA then reads a free-queue descriptor (either by reading a single descriptor or a burst
4) The receive DMA starts storing packet data in the previously free buffer data space by writing it out
5) When the receive DMA realizes that the current data buffer is filled (by knowing the buffer size it
6) The receive DMA then writes the previous packet descriptor and creates a linked list by placing the
7) This continues until the entire packet data is stored.
8) The receive DMA either waits until a packet has been completely received or until a programmable
Packet
Free Queue
Done Queue
DESCRIPTORS
the PCI bus.
a small buffer.
of descriptors), indicating where, in main memory, there exists some free data buffer space and
where the associated free packet descriptor resides.
through the PCI bus.
can calculate this), it then reads another free-queue descriptor to find another free data buffer and
packet descriptor location.
current descriptor in the next descriptor pointer field; it then starts filling the new buffer location.
Figure 9-1
number (from 1 to 7) of data buffers have been filled before writing the done-queue descriptor, which
indicates to the host that packet data is ready for processing.
provides an example of packet descriptors being link listed together (see channel 2).
A dedicated area of memory that describes the location and attributes of
the packet data.
A dedicated area of memory that the host writes to inform the DMA
where to store incoming packet data.
A dedicated area of memory that the DMA writes to inform the host
that the packet data is ready for processing.
9.2.3
and
9.2.4
for more details about this feature.
86 of 183
FUNCTION
SECTION
9.2.2
9.2.3
9.2.4