DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 66

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Bit #
Name
Default
Bit #
Name
Default
Bit 1/BERT Error Counter Overflow (BECO). A latched bit that is set when the 24-bit BERT error counter
(BEC) overflows. Cleared when read and is not set again until another overflow occurs.
Bit 2/BERT Bit Counter Overflow (BBCO). A latched bit that is set when the 32-bit BERT bit counter (BBC)
overflows. Cleared when read and is not set again until another overflow occurs.
Bit 3/Bit Error Detected (BED). A latched bit that is set when a bit error is detected. The receive BERT must be
in synchronization for it to detect bit errors. Cleared when read.
Bit 4/Receive Loss of Synchronization (RLOS). A latched bit that is set whenever the receive BERT begins
searching for a pattern. Once synchronization is achieved, this bit remains set until read.
Bit 5/Receive All Zeros (RA0). A latched bit that is set when 31 consecutive 0s are received. Allowed to be
cleared once a 1 is received.
Bit 6/Receive All Ones (RA1). A latched bit that is set when 31 consecutive 1s are received. Allowed to be
cleared once 0 is received.
Bits 8 to 15/BERT 24-Bit Error Counter (BEC). Lower word of the 24-bit error counter. See the BERTEC1
register description for details.
Register Name:
Register Description:
Register Address:
Note: Bits that are underlined are read-only; all other bits are read-write. default value for all bits is 0.
Bits 0 to 15/BERT 24-Bit Error Counter (BEC). Upper two words of the 24-bit error counter. This 24-bit
counter increments for each data bit received in error. This counter is not disabled when the receive BERT loses
synchronization. This counter is loaded with the current bit count value when the LC control bit in the BERTC0
register is toggled from low (0) to high (1). When full, this counter saturates and sets the BECO status bit.
15
7
0
0
BERTEC1
BERT 24-Bit Error Counter (upper)
051Ch
14
6
0
0
13
BERT 24-Bit Error Counter (upper byte)
5
0
0
BERT 24-Bit Error Counter
12
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4
0
0
11
3
0
0
10
0
2
0
1
0
9
0
0
0
8
0