DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 113

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

descriptor pointer and PV fields in the packet descriptor to 0 to ready them for transmission). The second
option allows the software a cleaner error-recovery technique. See
Figure 9-14. Transmit DMA Error Recovery Algorithm
Host Actions
The host typically handles the transmit DMA as follows:
1) The host places readied packets into the pending queue.
2) The host either polls (or is interrupted) that some outgoing packets have completed transmission and
3) If done queue reports that an error was incurred and that a packet was not transmitted, the host must
Transmit DMA Actions
A typical scenario for the transmit DMA is as follows:
1) The transmit DMA constantly reads the pending queue looking for packets that are queued for
2) The transmit DMA updates the done queue as packets or data buffers to complete transmission.
3) If an error occurs, the transmit DMA disables the channel and waits for the host to request that the
that it should read the done queue.
requeue the packet for transmission.
transmission.
channel be enabled.
Data Buffers and
Packet Descriptor
Space Available
for Reuse
No
Place the Errored Packet
Pending Descriptor Pointer
Descriptor Back into the
Fields to 0 in the Errored
Set the PV and the Next
the Next Descriptor
Set CHRST = 1 for
Pending Queue for
Read Done Queue
113 of 183
Pending Queue
Retransmission
Packet Descriptor
Written to the
Status = 1xx?
Yes
Figure 9-14
for more details.