DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 119

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

read pointer, and sets the status bit for transmit DMA pending-queue read (TPQR) in the status register
for DMA (SDMA). See Section
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0/Transmit Pending-Queue FIFO Enable (TPQFE). This bit must be set to 1 to enable the DMA to burst
read descriptors from the pending queue. If this bit is set to 0, descriptors are read one at a time.
Bit 1/Transmit Pending-Queue FIFO Flush (TPQF). When this bit is set to 1, the internal pending-queue FIFO
is flushed (currently loaded pending-queue descriptors are lost). This bit must be set to 0 for proper operation.
Bit 2/Transmit Done-Queue FIFO Enable (TDQFE). See Section
Bit 3/Transmit Done-Queue FIFO Flush (TDQF). See Section
Bits 8 to 10/Transmit Done-Queue Status Bit Threshold Setting (TDQT0 to TDQT2). See Section
more details.
0 = pending-queue burst read disabled
1 = pending-queue burst read enabled
0 = FIFO in normal operation
1 = FIFO is flushed
n/a
n/a
15
7
0
0
TDMAQ
Transmit DMA Queues Control
0880h
n/a
n/a
14
6
0
0
5
for more details about status bits.
n/a
n/a
13
5
0
0
119 of 183
n/a
n/a
12
4
0
0
TDQF
9.3.4
n/a
11
3
0
0
9.3.4
for details.
for details.
TDQFE
TDQT2
10
2
0
0
TDQT1
TPQF
1
0
9
0
TDQT0
TPQFE
0
0
8
0
9.3.4
for