DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 118

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Figure 9-18. Transmit Pending-Queue Structure
Once the transmit DMA is activated (by setting the TDE control bit in the master configuration register;
see Section 5), it can begin reading data out of the pending queue. It knows where to read the data by
reading the read pointer and adding it to the base address to obtain the actual 32-bit address. Once the
DMA has read the pending queue, it increments the read pointer by one dword. A check must be made to
ensure the incremented address does not exceed the transmit pending-queue end address. If the
incremented address does exceed this address, the incremented read pointer is set equal to 0000h.
Status/Interrupts
On each read of the pending queue by the DMA, the DMA sets the status bit for transmit DMA pending-
queue read (TPQR) in the status register for DMA (SDMA). The status bits can also (if enabled) cause
an hardware interrupt to occur. See Section
Pending-Queue Burst Reading
The DMA can read the pending queue in bursts, which allows for a more efficient use of the PCI bus.
The DMA can grab descriptors from the pending queue in groups rather than one at a time, freeing up
the PCI bus for more time-critical functions.
An internal FIFO can store up to 16 pending-queue descriptors (16 dwords, since each descriptor
occupies one dword). The host must configure the pending-queue FIFO for proper operation through the
transmit DMA queues-control (TDMAQ) register (see the following).
When enabled through the transmit pending-queue FIFO-enable (TPQFE) bit, the pending-queue FIFO
does not read the pending queue until it is empty. When the pending queue is empty, it attempts to fill
the FIFO with additional descriptors by burst reading the pending queue. Before it reads the pending
queue, it checks (by examining the transmit pending-queue host write pointer) to ensure the pending
queue contains enough descriptors to fill the pending-queue FIFO. If the pending queue does not have
enough descriptors to fill the FIFO, it only reads enough to empty the pending queue. If the FIFO detects
that there are no pending-queue descriptors available for it to read, it waits and tries again later. If the
pending-queue FIFO can read descriptors from the pending queue, it burst reads them, increments the
Pending-Queue Host Write Pointer
Pending-Queue DMA Read Pointer
Maximum of 65,536
Pending-Queue Descriptors
Base + End Address
5
for more details.
Base + 00h
Base + 04h
Base + 08h
Base + 0Ch
Base + 10h
Base + 14h
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Pending-Queue Descriptor
Pending-Queue Descriptor
Pending-Queue Descriptor
Pending-Queue Descriptor
Pending-Queue Descriptor
Pending-Queue Descriptor
Pending-Queue Descriptor
Host Readied
Host Readied
DMA Acquired
DMA Acquired
Host Readied
Host Readied
DMA Acquired