DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 144

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DS31256 256-Channel, High-Throughput HDLC Controller
10.2.4
Status Bits (PCMD1)
The upper word in the PCMD1 register is the status portion, which reports events as they occur. As mentioned
earlier, reads of the status portion occur normally, but writes are unique in that bits can only be reset (i.e., forced to
0). This occurs when a 1 is written to a bit position. Writes with a 0 to a bit position have no effect. This allows
individual bits to be reset.
Bits 16 to 20/Reserved. These read-only bits are forced to 0 by the device.
Bit 21/66MHz Capable (66MHz). This read-only bit is forced to 0 by the device to indicate that it is not capable
of running at 66MHz.
Bit 22/User-Definable Features Capable (UDF). This read-only bit is forced to 0 by the device to indicate that it
does not support user-definable features.
Bit 23/Fast Back-to-Back Capable Target (FBBCT). This read-only bit is forced to 1 by the device to indicate
that it is capable of accepting fast back-to-back transactions when the transactions are not from the same agent.
Bit 24/PCI Parity Error Reported (PARR). This read-only bit is forced to 0 by the device since the device
cannot act as a bus master.
Bits 25, 26/Device Timing Select Bits 0 and 1 (DTS0 and DTS1). These read-only bits are forced to 01b by the
device to indicate that they are capable of the medium timing requirements for the PDEVSEL signal.
Bit 27/Target Abort Initiated (TABT). This read/write bit is set to 1 when the device terminates a bus
transaction with a target abort. This occurs only when the local bus is operating in the bus arbitration mode and the
local bus does not have bus control when the host requests access. This bit can be reset (set to 0) by the host by
writing a 1 to this bit.
Bit 28/Target Abort Detected by Master (TABTM). This read-only bit is forced to 0 by the device since the
device cannot act as a bus master.
Bit 29/Master Abort (MABT). This read-only bit is forced to 0 by the device since the device cannot act as a bus
master.
Bit 30/PCI System Error Reported (PSE). This read/write bit is set to 1 when the device asserts the PSERR
signal (even if it is disabled through the PSEC command bit). This bit can be reset (set to 0) by the host by writing
1 to this bit.
Bit 31/PCI Parity Error Reported (PPE). This read/write bit is set to 1 when the device detects a parity error.
The host can reset this bit (set to 0) by writing a 1 to this bit.
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