ISP1161ABM ST-Ericsson Inc, ISP1161ABM Datasheet - Page 18

• Manufacturer Part Number: ISP1161ABM
• Description: IC USB HOST/DEVICE CTRLR 64-LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1161ABM

• Controller Type: USB 2.0 Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3150

Philips Semiconductors
9397 750 13962
Product data
8.5 FIFO buffer RAM access by DMA mode
The DMA interface between a microprocessor and the ISP1161A is shown in
Figure
When doing a DMA transfer, at the beginning of every burst the ISP1161A outputs a
DMA request to the microprocessor via the DREQ pin (DREQ1 for HC, DREQ2 for
DC). After receiving this signal, the microprocessor will reply with a DMA
acknowledge via the DACK pin (DACK1 for HC, DACK2 for DC), and at the same
time, execute the DMA transfer through the data bus. In the DMA mode, the
microprocessor must issue a read or write signal to the ISP1161A RD or WR pin. The
ISP1161A will repeat the DMA cycles until it receives an EOT signal to terminate the
DMA transfer.
ISP1161A supports both external and internal EOT signals. The external EOT signal
is received as input on pin EOT, and generally comes from the external
microprocessor. The internal EOT signal is generated by the ISP1161A internally.
To select either EOT method, set the appropriate DMA configuration register (see
Section 10.4.2
DMACounterSelect bit of the HcDMAConfiguration register (21H - read, A1H - write)
to logic 1 will enable the DMA counter for DMA transfer. When the DMA counter
reaches the value of the HcTransferCounter register, the internal EOT signal will be
generated to terminate the DMA transfer.
ISP1161A supports either single-cycle DMA operation or burst mode DMA operation.
Fig 17. DMA transfer in single-cycle mode.
N = 1/2 byte count of transfer data.
9.
RD or WR
D [ 15:0 ]
DREQ
DACK
EOT
and
Rev. 03 — 23 December 2004
Section
data #1
Full-speed USB single-chip host and device controller
13.1.6). For example, for the HC, setting
data #2
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
data #N
ISP1161A
004aaa103
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