ISP1161ABM ST-Ericsson Inc, ISP1161ABM Datasheet - Page 37

• Manufacturer Part Number: ISP1161ABM
• Description: IC USB HOST/DEVICE CTRLR 64-LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1161ABM

• Controller Type: USB 2.0 Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3150

Philips Semiconductors
9397 750 13962
Product data
end of the frame for full-speed and low-speed packets. By programming these fields,
the effective USB bus usage can be changed. Furthermore, the size of the ITL buffers
(HcITLBufferLength, 2AH - read, AAH - write) is programmed.
In the case when a USB frame contains both ISO and AT packets, two interrupts will
be generated per frame.
One interrupt is issued concurrently with the SOF. This interrupt (the ITLint bit is set in
the HcµPInterrupt register) triggers reading and writing of the ITL buffer by the
microprocessor, after which the interrupt is cleared by the microprocessor.
Next the programmable ATL Interrupt (the ATLint bit is set in the HcµPInterrupt
register) is issued, which triggers reading and writing of the ATL buffer by the
microprocessor, after which the interrupt is cleared by the microprocessor. If the
microprocessor cannot handle the ISO interrupt before the next ISO interrupt,
disrupted ISO traffic can result.
To be able to send more than one packet to the same Control or Bulk endpoint in the
same frame, an Active bit and a TotalBytes field are introduced (see
Active bit is cleared only if all data of the Philips Transfer Descriptor (PTD) has been
transferred or if a transaction at that endpoint contained a fatal error. If all PTDs of the
ATL are serviced, and the frame is not over yet, the HC starts looking for a PTD with
the Active bit still set. If such a PTD is found and there is still enough time in this
frame, another transaction is started on the USB bus for this endpoint.
For ISO processing, the HCD also has to take care of the HCBufferStatus register
(2CH, read only) for the ITL buffer RAM operations. After the HCD writes ISO data
into ITL buffer RAM, the ITL0BufferFull or ITL1BufferFull bit (depends if it is ITL0 or
ITL1) will be set to logic 1.
After the HC processes the ISO data in the ITL buffer RAM, the corresponding
ITL0BufferDone or ITL1BufferDone bit will automatically be set to logic 1.The HCD
can clear the buffer status bits by a read of the ITL buffer RAM. This must be done
within the 1 ms frame from which the ITL0BufferDone or ITL1BufferDone was set.
For example, the HCD writes ISO_A data into the ITL0 buffer in the first frame. This
will cause the HCBufferStatus register to show that the ITL0 buffer is full by setting
the ITL0BufferFull bit to logic 1. At this stage the HCD cannot write ISO data into the
ITL0 buffer RAM again.
In the second frame, the HC will process the ISO-A data in the ITL0 buffer. At the
same time, the HCD can write ISO-B data into ITL1 buffer. When the next SOF
comes (the beginning of the third frame), both the ITL1BufferFull and ITL0BufferDone
are automatically set to logic 1.
In the third frame the HCD has to read at least two bytes (one word) of the ITL0 buffer
to clear both the ITL0BufferFull and ITL0BufferDone bits. If both are not cleared,
when the next SOF comes (the beginning of the fourth frame) the ITL0BufferDone
and ITL0BufferFull bits will be cleared automatically. This also applies to the ITL1
buffer because the ITL0 and ITL1 are Ping-Pong structured buffers. To recover from
this state, a power-on reset or software reset will have to be applied.
Rev. 03 — 23 December 2004
Full-speed USB single-chip host and device controller
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
ISP1161A
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