ISP1161ABM ST-Ericsson Inc, ISP1161ABM Datasheet - Page 49

• Manufacturer Part Number: ISP1161ABM
• Description: IC USB HOST/DEVICE CTRLR 64-LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1161ABM

• Controller Type: USB 2.0 Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3150

Philips Semiconductors
Table 14:
9397 750 13962
Product data
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcInteruptStatus register: bit allocation
R/W
R/W
R/W
31
23
15
0
0
0
10.1.4 HcInterruptStatus register (R/W: 03H/83H)
Table 13:
This register provides the status of the events that cause hardware interrupts. When
an event occurs, the HC sets the corresponding bit in this register. When a bit is set, a
hardware interrupt is generated if the interrupt is enabled in the HcInterruptEnable
register (see
clear individual bits in this register by writing logic 1 to the bit positions to be cleared,
but cannot set any of these bits. Conversely, the HC can set bits in this register, but
cannot clear the bits.
Code (Hex): 03 — read
Code (Hex): 83 — write
Bit
31 to 18
17 to 16
15 to 1
0
R/W
R/W
R/W
30
22
14
0
0
0
HcCommandStatus register: bit description
Symbol
-
SOC[1:0]
-
HCR
Section
R/W
R/W
R/W
29
21
13
0
0
0
Rev. 03 — 23 December 2004
10.1.5) and the MasterInterruptEnable bit is set. The HCD can
Description
reserved
SchedulingOverrunCount: The field is incremented on each
scheduling overrun error. It is initialized to 00B and wraps around
at 11B. It will be incremented when a scheduling overrun is
detected even if SchedulingOverrun in HcInterruptStatus has
already been set. This is used by HCD to monitor any persistent
scheduling problems.
reserved
HostControllerReset: This bit is set by the HCD to initiate a
software reset of the HC. Regardless of the functional state of HC,
it moves to the USBSuspend state in which most of the operational
registers are reset, except those stated otherwise, and no Host
bus accesses are allowed. This bit is cleared by HC upon the
completion of the reset operation. The reset operation must be
completed within 10 µs. This bit, when set, does not cause a reset
to the Root Hub and no subsequent reset signaling will be
asserted to its downstream ports.
Full-speed USB single-chip host and device controller
R/W
R/W
R/W
28
20
12
0
0
0
reserved
reserved
reserved
R/W
R/W
R/W
27
19
11
0
0
0
R/W
R/W
R/W
26
18
10
0
0
0
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
ISP1161A
R/W
R/W
R/W
25
17
0
0
9
0
R/W
R/W
R/W
48 of 134
24
16
0
0
8
0