SAB82532H10V32A Infineon Technologies, SAB82532H10V32A Datasheet - Page 115

• Manufacturer Part Number: SAB82532H10V32A
• Description: IC CONTROLLER 2-CH SER 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of SAB82532H10V32A

• Controller Type: Serial Communications Controller (SCC)
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 8mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-SQFP
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Other names: SAB82532H10V32A; SAB82532H10V32AIN

Transmit FIFO (XFIFO)
Access: write
Writing data to the XFIFO can be done in 8-bit (byte) or 16-bit (word) access depending
on the selected bus interface mode. The LSB is transmitted first.
• Interrupt Mode
• DMA Mode
Note: Addresses within the address space of the FIFO’s all point to the current data
Status Register (STAR)
Access: read
Value after RESET: 48
XDOV …
XFW …
Semiconductor Group
Selected if DMA bit in XBCH is set to ‘zero’.
Up to 32 bytes/16 words of transmit data can be written to the XFIFO following an XPR
(or ALLS) interrupt.
Selected if DMA bit in XBCH is set to ‘one’.
Prior to any data transfer, the actual byte count of the frame to be transmitted must
be written to the XBCH, XBCL registers by the user.
If data transfer is then initiated via the CMDR register (command XTF or XIF), the
ESCC2 autonomously requests the correct amount of block data transfers
(n
STAR
word/byte, i.e. the current data byte can be accessed with any address within the
32-byte range.
In HDLC mode (no extended transparent mode) 32 bytes have to be written to the
FIFO when only XTF command is set afterwards. There is no restriction when XTF
and XME command is set afterwards.
BW + Remainder; BW = 32 or 16; n = 0, 1, …).
XDOV
7
Transmit Data Overflow
More than 32 bytes have been written to the XFIFO.
This bit is reset by:
– a transmitter reset command XRES
– or when all bytes in the accessible half of the XFIFO have been
Transmit FIFO Write Enable
Data can be written to the XFIFO.
H
moved into the inaccessible half.
XFW
address: ch-A: 00 ... 1F
address: ch-A: 20
XRNR RRNR
ch-B: 40 ... 5F
ch-B: 60
115
H
H
H
H
RLI
Detailed Register Description
SAB 82532/SAF 82532
CEC
CTS
HDLC Mode
WFA
07.96
0