PIC18F4550-I/P Microchip Technology Inc., PIC18F4550-I/P Datasheet - Page 114

• Manufacturer Part Number: PIC18F4550-I/P
• Description: 40 PIN, 32 KB FLASH, 2048 RAM, FS-USB 2.0
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4550-I/P

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 12 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 34
• Interface: I2C/SPI/UART/USART/USB
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 48 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2455/2550/4455/4550
TABLE 10-1:
DS39632C-page 112
RA0/AN0
RA1/AN1
RA2/AN2/
V
RA3/AN3/
V
RA4/T0CKI/
C1OUT/RCV
RA5/AN4/SS/
HLVDIN/C2OUT
OSC2/CLKO/
RA6
Legend:
REF
REF
-/CV
+
Pin
REF
OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
Function
HLVDIN
C1OUT
C2OUT
PORTA I/O SUMMARY
CV
V
T0CKI
OSC2
CLKO
V
RCV
RA0
AN0
RA1
AN1
RA2
AN2
RA3
AN3
RA4
RA5
AN4
RA6
REF
SS
REF
REF
+
-
Setting
TRIS
0
1
1
0
1
1
0
1
1
1
x
0
1
1
1
0
1
1
0
x
0
1
1
1
1
0
x
x
0
1
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
I/O
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
I/O Type
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
DIG
TTL
DIG
TTL
DIG
TTL
DIG
TTL
DIG
DIG
TTL
DIG
TTL
TTL
DIG
DIG
DIG
TTL
ST
ST
Preliminary
LATA<0> data output; not affected by analog input.
PORTA<0> data input; disabled when analog input enabled.
A/D input channel 0 and Comparator C1- input. Default configuration
on POR; does not affect digital output.
LATA<1> data output; not affected by analog input.
PORTA<1> data input; reads ‘0’ on POR.
A/D input channel 1 and Comparator C2- input. Default configuration
on POR; does not affect digital output.
LATA<2> data output; not affected by analog input. Disabled when
CV
PORTA<2> data input. Disabled when analog functions enabled;
disabled when CV
A/D input channel 2 and Comparator C2+ input. Default configuration
on POR; not affected by analog output.
A/D and comparator voltage reference low input.
Comparator voltage reference output. Enabling this feature disables
digital I/O.
LATA<3> data output; not affected by analog input.
PORTA<3> data input; disabled when analog input enabled.
A/D input channel 3 and Comparator C1+ input. Default configuration
on POR.
A/D and comparator voltage reference high input.
LATA<4> data output; not affected by analog input.
PORTA<4> data input; disabled when analog input enabled.
Timer0 clock input.
Comparator 1 output; takes priority over port data.
External USB transceiver RCV input.
LATA<5> data output; not affected by analog input.
PORTA<5> data input; disabled when analog input enabled.
A/D input channel 4. Default configuration on POR.
Slave select input for SSP (MSSP module).
High/Low-Voltage Detect external trip point input.
Comparator 2 output; takes priority over port data.
Main oscillator feedback output connection (all XT and HS modes).
System cycle clock output (F
INTCKO modes.
LATA<6> data output. Available only in ECIO, ECPIO and INTIO
modes; otherwise, reads as ‘0’.
PORTA<6> data input. Available only in ECIO, ECPIO and INTIO
modes; otherwise, reads as ‘0’.
REF
output enabled.
REF
output enabled.
Description
OSC
/4); available in EC, ECPLL and
© 2006 Microchip Technology Inc.