PIC18F4550-I/P Microchip Technology Inc., PIC18F4550-I/P Datasheet - Page 153

• Manufacturer Part Number: PIC18F4550-I/P
• Description: 40 PIN, 32 KB FLASH, 2048 RAM, FS-USB 2.0
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4550-I/P

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 12 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 34
• Interface: I2C/SPI/UART/USART/USB
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 48 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

16.4
The Enhanced PWM mode provides additional PWM
output options for a broader range of control applica-
tions. The module is a backward compatible version of
the standard CCP module and offers up to four outputs,
designated P1A through P1D. Users are also able to
select the polarity of the signal (either active-high or
active-low). The module’s output mode and polarity are
configured
CCP1M3:CCP1M0 bits of the CCP1CON register.
Figure 16-1 shows a simplified block diagram of PWM
operation. All control registers are double-buffered and
are loaded at the beginning of a new PWM cycle (the
period boundary when Timer2 resets) in order to
prevent glitches on any of the outputs. The exception is
the PWM Dead-Band Delay register, ECCP1DEL,
which is loaded at either the duty cycle boundary or the
boundary period (whichever comes first). Because of
the buffering, the module waits until the assigned timer
resets instead of starting immediately. This means that
Enhanced PWM waveforms do not exactly match the
standard PWM waveforms, but are instead offset by
one full instruction cycle (4 T
As before, the user must manually configure the
appropriate TRIS bits for output.
FIGURE 16-1:
© 2006 Microchip Technology Inc.
Enhanced PWM Mode
Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time
CCPR1H (Slave)
Duty Cycle Registers
Comparator
by
CCPR1L
PR2
base.
TMR2
Comparator
setting
SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE
(Note 1)
OSC
the
Clear Timer,
set CCP1 pin and
latch D.C.
CCP1CON<5:4>
).
P1M1:P1M0
R
S
PIC18F2455/2550/4455/4550
P1M1:P1M0
Q
and
Preliminary
ECCP1DEL
Controller
Output
16.4.1
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following equation:
EQUATION 16-1:
PWM frequency is defined as 1/ [PWM period]. When
TMR2 is equal to PR2, the following three events occur
on the next increment cycle:
• TMR2 is cleared
• The CCP1 pin is set (if PWM duty cycle = 0%, the
• The PWM duty cycle is copied from CCPR1L into
2
CCP1/P1A
CCP1 pin will not be set)
CCPR1H
Note:
P1C
P1D
P1B
PWM Period = [(PR2) + 1] • 4 • T
4
CCP1M3:CCP1M0
PWM PERIOD
The Timer2 postscaler (see Section 13.0
“Timer2 Module”) is not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
TRISD<4>
TRISD<5>
TRISD<6>
TRISD<7>
(TMR2 Prescale Value)
CCP1/P1A
P1B
P1C
P1D
DS39632C-page 151
OSC
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