PIC18F4550-I/P Microchip Technology Inc., PIC18F4550-I/P Datasheet - Page 294

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PIC18F4550-I/P

Manufacturer Part Number
PIC18F4550-I/P
Description
40 PIN, 32 KB FLASH, 2048 RAM, FS-USB 2.0
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC18F4550-I/P

A/d Inputs
13-Channel, 10-Bit
Comparators
2
Cpu Speed
12 MIPS
Eeprom Memory
256 Bytes
Input Output
34
Interface
I2C/SPI/UART/USART/USB
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
32K Bytes
Ram Size
2K Bytes
Speed
48 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

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PIC18F2455/2550/4455/4550
REGISTER 25-6:
DS39632C-page 292
bit 7
Legend:
R = Readable bit
-n = Value when device is unprogrammed
bit 7
bit 6
bit 5
bit 4-3
bit 2
bit 1
bit 0
Note 1:
DEBUG
R/P-1
Available only on PIC18F4455/4550 devices in 44-pin TQFP packages. Always leave this bit clear in all
other devices.
DEBUG: Background Debugger Enable bit
1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
0 = Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
XINST: Extended Instruction Set Enable bit
1 = Instruction set extension and Indexed Addressing mode enabled
0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
ICPRT: Dedicated In-Circuit Debug/Programming Port (ICPORT) Enable bit
1 = ICPORT enabled
0 = ICPORT disabled
Unimplemented: Read as ‘0’
LVP: Single-Supply ICSP™ Enable bit
1 = Single-Supply ICSP enabled
0 = Single-Supply ICSP disabled
Unimplemented: Read as ‘0’
STVREN: Stack Full/Underflow Reset Enable bit
1 = Stack full/underflow will cause Reset
0 = Stack full/underflow will not cause Reset
XINST
R/P-0
CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h)
P = Programmable bit
ICPRT
R/P-0
(1)
U-0
Preliminary
u = Unchanged from programmed state
U = Unimplemented bit, read as ‘0’
U-0
R/P-1
LVP
© 2006 Microchip Technology Inc.
(1)
U-0
STVREN
R/P-1
bit 0

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