PIC18F4550-I/P Microchip Technology Inc., PIC18F4550-I/P Datasheet - Page 120

• Manufacturer Part Number: PIC18F4550-I/P
• Description: 40 PIN, 32 KB FLASH, 2048 RAM, FS-USB 2.0
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4550-I/P

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 12 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 34
• Interface: I2C/SPI/UART/USART/USB
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 48 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2455/2550/4455/4550
TABLE 10-5:
DS39632C-page 118
RC0/T1OSO/
T13CKI
RC1/T1OSI/
CCP2/UOE
RC2/CCP1/
P1A
RC4/D-/VM
RC5/D+/VP
RC6/TX/CK
Legend:
Note 1:
Pin
2:
3:
OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, XCVR = USB transceiver, x = Don’t care (TRIS bit does not affect port direction or is overridden
for this option)
Default pin assignment. Alternate pin assignment is RB3 (when CCP2MX = 0).
RC4 and RC5 do not have corresponding TRISC bits. In Port mode, these pins are input only. USB data direction is
determined by the USB configuration.
40/44-pin devices only.
Function
PORTC I/O SUMMARY
CCP2
T1OSO
T13CKI
T1OSI
P1A
CCP1
UOE
RC0
RC1
RC2
RC4
RC5
RC6
VM
D+
VP
TX
CK
D-
(3)
(1)
Setting
TRIS
—
—
—
—
—
—
—
—
0
1
x
1
0
1
x
0
1
0
0
1
0
1
0
0
1
0
0
1
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
I/O
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
I/O Type
XCVR
XCVR
XCVR
XCVR
ANA
ANA
TTL
TTL
TTL
TTL
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
ST
ST
ST
ST
ST
ST
ST
ST
Preliminary
LATC<0> data output.
PORTC<0> data input.
Timer1 oscillator output; enabled when Timer1 oscillator enabled.
Disables digital I/O.
Timer1/Timer3 counter input.
LATC<1> data output.
PORTC<1> data input.
Timer1 oscillator input; enabled when Timer1 oscillator enabled.
Disables digital I/O.
CCP2 Compare and PWM output; takes priority over port data.
CCP2 Capture input.
External USB transceiver OE output.
LATC<2> data output.
PORTC<2> data input.
ECCP1 Compare and PWM output; takes priority over port data.
ECCP1 Capture input.
ECCP1 Enhanced PWM output, channel A; takes priority over port
data. May be configured for tri-state during Enhanced PWM shutdown
events.
PORTC<4> data input; disabled when USB module or on-chip
transceiver are enabled.
USB bus differential minus line output (internal transceiver).
USB bus differential minus line input (internal transceiver).
External USB transceiver VM input.
PORTC<5> data input; disabled when USB module or on-chip
transceiver are enabled.
USB bus differential plus line output (internal transceiver).
USB bus differential plus line input (internal transceiver).
External USB transceiver VP input.
LATC<6> data output.
PORTC<6> data input.
Asynchronous serial transmit data output (EUSART module); takes
priority over port data. User must configure as output.
Synchronous serial clock output (EUSART module); takes priority
over port data.
Synchronous serial clock input (EUSART module).
Description
© 2006 Microchip Technology Inc.