PIC18F4550-I/P Microchip Technology Inc., PIC18F4550-I/P Datasheet - Page 305

• Manufacturer Part Number: PIC18F4550-I/P
• Description: 40 PIN, 32 KB FLASH, 2048 RAM, FS-USB 2.0
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4550-I/P

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 12 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 34
• Interface: I2C/SPI/UART/USART/USB
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 48 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

25.5.1
The program memory may be read to or written from
any location using the table read and table write
instructions. The device ID may be read with table
reads. The Configuration registers may be read and
written with the table read and table write instructions.
In normal execution mode, the CPn bits have no direct
effect. CPn bits inhibit external reads and writes. A
block of user memory may be protected from table
writes if the WRTn Configuration bit is ‘0’. The EBTRn
bits control table reads. For a block of user memory
with the EBTRn bit set to ‘0’, a table read instruction
that executes from within that block is allowed to read.
FIGURE 25-6:
© 2006 Microchip Technology Inc.
Results: All table writes disabled to Blockn whenever WRTn = 0.
TBLPTR = 0008FFh
Register Values
PC = 001FFEh
PC = 005FFEh
PROGRAM MEMORY
CODE PROTECTION
TABLE WRITE (WRTn) DISALLOWED
PIC18F2455/2550/4455/4550
Program Memory
Preliminary
TBLWT*
TBLWT*
A table read instruction that executes from a location
outside of that block is not allowed to read and will
result in reading ‘0’s. Figures 25-6 through 25-8
illustrate table write and table read protection.
Note:
000000h
0007FFh
000800h
001FFFh
002000h
003FFFh
004000h
005FFFh
006000h
007FFFh
Code protection bits may only be written to
a ‘0’ from a ‘1’ state. It is not possible to
write a ‘1’ to a bit in the ‘0’ state. Code
protection bits are only set to ‘1’ by a full
Chip Erase or Block Erase function. The
full Chip Erase and Block Erase functions
can only be initiated via ICSP operation or
an external programmer.
Configuration Bit Settings
WRTB, EBTRB = 11
WRT0, EBTR0 = 01
WRT1, EBTR1 = 11
WRT2, EBTR2 = 11
WRT3, EBTR3 = 11
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