PIC18F4550-I/P Microchip Technology Inc., PIC18F4550-I/P Datasheet - Page 269

• Manufacturer Part Number: PIC18F4550-I/P
• Description: 40 PIN, 32 KB FLASH, 2048 RAM, FS-USB 2.0
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4550-I/P

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 12 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 34
• Interface: I2C/SPI/UART/USART/USB
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 48 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

21.6
Figure 21-4 shows the operation of the A/D converter
after the GO/DONE bit has been set and the
ACQT2:ACQT0 bits are cleared. A conversion is
started after the following instruction to allow entry into
Sleep mode before the conversion begins.
Figure 21-5 shows the operation of the A/D converter
after
ACQT2:ACQT0 bits are set to ‘010’ and selecting a
4 T
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D Result register
pair will NOT be updated with the partially completed
A/D
ADRESH:ADRESL registers will continue to contain
the value of the last completed conversion (or the last
value written to the ADRESH:ADRESL registers).
FIGURE 21-4:
FIGURE 21-5:
© 2006 Microchip Technology Inc.
(Holding capacitor continues
acquiring input)
Set GO/DONE bit
AD
1
acquisition time before the conversion starts.
the
T
conversion
Set GO/DONE bit
CY
A/D Conversions
Holding capacitor is disconnected from analog input (typically 100 ns)
T
ACQ
Acquisition
- T
Automatic
2
GO/DONE
Time
AD
Conversion starts
Cycles
T
AD
3
1 T
sample.
A/D CONVERSION T
A/D CONVERSION T
AD
b9
4
bit
2 T
Conversion starts
(Holding capacitor is disconnected)
has
AD
b8
1
This
3 T
been
AD
b9
b7
2
means
4 T
set,
PIC18F2455/2550/4455/4550
AD
On the following cycle:
ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
b8
3
b6
AD
AD
5 T
On the following cycle:
ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
CYCLES (ACQT<2:0> = 000, T
CYCLES (ACQT<2:0> = 010, T
Preliminary
the
the
AD
b5
b7
4
6 T
AD
T
b4
5
b6
AD
7 T
Cycles
After the A/D conversion is completed or aborted, a
2 T
started. After this wait, acquisition on the selected
channel is automatically started.
21.7
The discharge phase is used to initialize the value of
the capacitor array. The array is discharged before
every sample. This feature helps to optimize the
unity-gain amplifier as the circuit always needs to
charge
charge/discharge based on previous measurement
values.
AD
Note:
b3
b5
6
AD
8
wait is required before the next acquisition can be
T
AD
b4
Discharge
b2
7
the
9 T
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
AD
b3
b1
8
10
capacitor
T
AD
b0
ACQ
b2
9
ACQ
11
= 0)
T
AD
= 4 T
10
Discharge
b1
array,
1
AD
DS39632C-page 267
b0
11
)
rather
T
Discharge
AD
1
than