IDT82V2088BBG IDT, Integrated Device Technology Inc, IDT82V2088BBG Datasheet - Page 12

• Manufacturer Part Number: IDT82V2088BBG
• Description: IC LINE INTERFACE UNIT 208-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Line Interface Units (LIUs)r

Specifications of IDT82V2088BBG

• Protocol: E1
• Voltage - Supply: 3.13 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 208-PBGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 800-1705; 82V2088BBG

OCTAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
Table-1 Pin Description (Continued)
INT/MOT
MCLKS
MCLK
Name
SCLK
LOS1
LOS2
LOS3
LOS4
LOS5
LOS6
LOS7
LOS8
P/S
CS
Output
Input
Input
Input
Input
Input
Input
Type
PQFP208
17
56
14
12
45
46
1
3
4
5
6
7
8
9
Pin No.
PBGA208
G1
G4
R6
C2
C3
D1
D2
D3
E1
E2
E3
F2
N1
N2
MCLK: Master Clock
MCLK is an independent, free-running reference clock. It is a single reference for all operation modes
and provides selectable1.544 MHz or 37.056 MHz for T1/J1 operating mode while 2.048 MHz or
49.152 MHz for E1 operating mode.
The reference clock is used to generate several internal reference signals:
•
•
•
•
•
•
The loss of MCLK will turn all the eight TTIP/TRING into high impedance status.
MCLKS: Master Clock Select
If 2.048 MHz (E1) or 1.544 MHz (T1/J1) is selected as the MCLK, this pin should be connected to
ground; and if the 49.152 MHz (E1) or 37.056 MHz (T1/J1) is selected as the MCLK, this pin should
be pulled high.
LOSn: Loss of Signal Output for Channel 1~8
These pins are used to indicate the loss of received signals. When LOSn pin becomes high, it indicates
the loss of received signals in channel n. The LOSn pin will become low automatically when valid
received signal is detected again. The criteria of loss of signal are described in
DETECTION.
P/S: Parallel or Serial Control Interface Select
Level on this pin determines which control mode is selected to control the device as follows:
The serial microcontroller interface consists of CS, SCLK, SDI, SDO and SCLKE pins. Parallel micro-
controller interface consists of CS, A[7:0], D[7:0], DS/RD, R/W/WR pins. The device supports non-mul-
tiplexed parallel interfaces as follows:
INT/MOT: Intel or Motorola Microcontroller Interface Select
In microcontroller mode, the parallel microcontroller interface is configured for Motorola compatible
microcontrollers when this pin is low, or for Intel compatible microcontrollers when this pin is high.
CS: Chip Select
In serial and parallel microcontroller mode, this pin is asserted low by the microcontroller to enable
microcontroller interface. For each read or write operation, this pin must be changed from high to low,
and will remain low until the operation is over.
SCLK: Shift Clock
In serial microcontroller interface mode, signal on this pin is the shift clock for the serial interface. Con-
figuration data on pin SDI is sampled on the rising edges of SCLK. Configuration and status data on
pin SDO is clocked out of the device on the rising edges of SCLK if pin SCLKE is low, or on the falling
edges of SCLK if pin SCLKE is high.
Timing reference for the integrated clock recovery unit.
Timing reference for the integrated digital jitter attenuator.
Timing reference for microcontroller interface.
Generation of RCLKn signal during a loss of signal condition.
Reference clock during Transmit All Ones (TAO) and all zeros condition. When sending PRBS/
QRSS or Inband Loopback code, either MCLK or TCLKn can be selected as the reference clock.
Reference clock for ATAO and AIS.
High
Low
P/S
P/S, INT/MOT
Control Interface
10
11
12
Parallel Microcontroller Interface
Serial Microcontroller Interface
Control Interface
Microcontroller Interface
Motorola non-multiplexed
Intel non-multiplexed
Description
TEMPERATURE RANGES
3.5 LOS AND AIS
INDUSTRIAL