IDT82V2088BBG IDT, Integrated Device Technology Inc, IDT82V2088BBG Datasheet - Page 4

• Manufacturer Part Number: IDT82V2088BBG
• Description: IC LINE INTERFACE UNIT 208-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Line Interface Units (LIUs)r

Specifications of IDT82V2088BBG

• Protocol: E1
• Voltage - Supply: 3.13 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 208-PBGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 800-1705; 82V2088BBG

OCTAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
4
5
6
7
3.8
3.9
3.10
3.11
3.12
3.13
3.14
3.15
3.16
PROGRAMMING INFORMATION .............................................................................................. 37
4.1
4.2
IEEE STD 1149.1 JTAG TEST ACCESS PORT ........................................................................ 57
5.1
5.2
TEST SPECIFICATIONS ............................................................................................................ 61
MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS ......................................... 73
7.1
7.2
ERROR DETECTION/COUNTING AND INSERTION ...................................................... 31
3.8.1 DEFINITION OF LINE CODING ERROR ............................................................... 31
3.8.2 ERROR DETECTION AND COUNTING ................................................................ 31
3.8.3 BIPOLAR VIOLATION AND PRBS ERROR INSERTION ...................................... 32
LINE DRIVER FAILURE MONITORING ........................................................................... 32
MCLK AND TCLK ............................................................................................................. 33
3.10.1 MASTER CLOCK (MCLK) ...................................................................................... 33
3.10.2 TRANSMIT CLOCK (TCLK).................................................................................... 33
MICROCONTROLLER INTERFACES ............................................................................. 34
3.11.1 PARALLEL MICROCONTROLLER INTERFACE................................................... 34
3.11.2 SERIAL MICROCONTROLLER INTERFACE ........................................................ 34
INTERRUPT HANDLING .................................................................................................. 35
GENERAL PURPOSE I/O ................................................................................................ 36
5V TOLERANT I/O PINS .................................................................................................. 36
RESET OPERATION ........................................................................................................ 36
POWER SUPPLY ............................................................................................................. 36
REGISTER LIST AND MAP ............................................................................................. 37
REGISTER DESCRIPTION .............................................................................................. 39
4.2.1 GLOBAL REGISTERS............................................................................................ 39
4.2.2 JITTER ATTENUATION CONTROL REGISTER ................................................... 41
4.2.3 TRANSMIT PATH CONTROL REGISTERS........................................................... 41
4.2.4 RECEIVE PATH CONTROL REGISTERS ............................................................. 43
4.2.5 NETWORK DIAGNOSTICS CONTROL REGISTERS ........................................... 45
4.2.6 INTERRUPT CONTROL REGISTERS ................................................................... 48
4.2.7 LINE STATUS REGISTERS ................................................................................... 51
4.2.8 INTERRUPT STATUS REGISTERS ...................................................................... 54
4.2.9 COUNTER REGISTERS ........................................................................................ 55
4.2.10 TRANSMIT AND RECEIVE TERMINATION REGISTER ....................................... 56
JTAG INSTRUCTIONS AND INSTRUCTION REGISTER ............................................... 58
JTAG DATA REGISTER ................................................................................................... 58
5.2.1 DEVICE IDENTIFICATION REGISTER (IDR) ........................................................ 58
5.2.2 BYPASS REGISTER (BR)...................................................................................... 58
5.2.3 BOUNDARY SCAN REGISTER (BSR) .................................................................. 58
5.2.4 TEST ACCESS PORT CONTROLLER .................................................................. 59
SERIAL INTERFACE TIMING .......................................................................................... 73
PARALLEL INTERFACE TIMING ..................................................................................... 74
4
TEMPERATURE RANGES
INDUSTRIAL