ICS1893Y-10LFT IDT, Integrated Device Technology Inc, ICS1893Y-10LFT Datasheet - Page 108
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ICS1893Y-10LFT
Manufacturer Part Number
ICS1893Y-10LFT
Description
PHYCEIVER LOW PWR 3.3V 64-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
PHYceiver™r
Type
PHY Transceiverr
Specifications of ICS1893Y-10LFT
Protocol
MII
Voltage - Supply
3.14 V ~ 3.47 V
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Drivers/receivers
-
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Other names
1893Y-10LFT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ICS1893Y-10LFT
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
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ICS1893 Rev C 6/6/00
Table 9-3.
P2LI
P3TD
Name
Pin
ICS1893 Data Sheet - Release
Number
PHY Address and LED Pins
Pin
60
62
Input or
Input or
Output
Output
Type
Pin
Copyright © 2000, Integrated Circuit Systems, Inc.
All rights reserved.
PHY (Address Bit) 2 / Link Integrity LED.
For more information on this pin, see
As an input pin:
As an output pin:
PHY (Address Bit) 3 / Transmit Data LED.
For more information on this pin, see
As an input pin:
As an output pin:
Caution:
Caution:
•
•
•
•
•
•
This multi-function configuration pin is:
– An input pin during either a power-on reset or a hardware reset. In
– An output pin following reset. In this case, this pin provides link status
This pins establishes the address for the ICS1893. When the signal on
this pin is logic:
– Low, that address bit is set to logic zero.
– High, that address bit is set to logic one.
When the signal on this pin is:
– De-asserted, this state indicates the ICS1893 does not have a link.
– Asserted, this state indicates the ICS1893 has a valid link.
These multi-function configuration pins are:
– Input pins during either a power-on reset or a hardware reset. In this
– Output pins following reset. In this case, this pin provides link status
This pin establishes the address for the ICS1893. When the signal on
one of these pins is logic:
– Low, that address bit is set to logic zero.
– High, that address bit is set to logic one.
When the signal on this pin is:
– De-asserted, this state indicates the ICS1893 does not have a link.
– Asserted, this state indicates the ICS1893 has a valid link.
this case, this pin configures the address of the ICS1893 when it is in
either hardware mode or software mode.
for the ICS1893.
case, these pins configure the address of the ICS1893 when it is in
either hardware mode or software mode.
for the ICS1893.
This pin must not float. (See the notes at
“ Multi-Function (Multiplexed) Pins: PHY Address and LED
Pins”
This pin must not float. (See the notes at
“ Multi-Function (Multiplexed) Pins: PHY Address and LED
Pins”
108
.)
.)
Chapter 9 Pin Diagram, Listings, and Descriptions
Pin Description
Section 6.8, “ Status Interface”
Section 6.8, “ Status Interface”
Section 9.3.2,
Section 9.3.2,
June, 2000
.
.
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