ICS1893Y-10LFT IDT, Integrated Device Technology Inc, ICS1893Y-10LFT Datasheet - Page 6
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ICS1893Y-10LFT
Manufacturer Part Number
ICS1893Y-10LFT
Description
PHYCEIVER LOW PWR 3.3V 64-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
PHYceiver™r
Type
PHY Transceiverr
Specifications of ICS1893Y-10LFT
Protocol
MII
Voltage - Supply
3.14 V ~ 3.47 V
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Drivers/receivers
-
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Other names
1893Y-10LFT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ICS1893Y-10LFT
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
ICS1893 Rev C 6/6/00
Section
8.11
8.11.1
8.11.2
8.11.3
8.11.4
8.11.5
8.11.6
8.11.7
8.11.8
8.11.9
8.12
8.12.1
8.12.2
8.12.3
8.12.4
8.12.5
8.12.6
8.12.7
8.12.8
8.12.9
8.12.10
8.12.11
8.12.12
8.12.13
8.12.14
8.13
8.13.1
8.13.2
8.13.3
8.13.4
8.13.5
8.13.6
8.13.7
8.13.8
8.13.9
ICS1893 Data Sheet - Release
Register 16: Extended Control Register ................................................................ 88
Command Override Write Enable (bit 16.15) ......................................................... 89
ICS Reserved (bits 16.14:11) ................................................................................. 89
PHY Address (bits 16.10:6) ................................................................................... 89
Stream Cipher Scrambler Test Mode (bit 16.5) ..................................................... 89
ICS Reserved (bit 16.4) ......................................................................................... 89
NRZ/NRZI Encoding (bit 16.3) ............................................................................... 89
Invalid Error Code Test (bit 16.2) ........................................................................... 90
ICS Reserved (bit 16.1) ......................................................................................... 90
Stream Cipher Disable (bit 16.0) ............................................................................ 90
Register 17: Quick Poll Detailed Status Register ................................................... 91
Data Rate (bit 17.15) .............................................................................................. 92
Duplex (bit 17.14) ................................................................................................... 92
Auto-Negotiation Progress Monitor (bits 17.13:11) ................................................ 93
100Base-TX Receive Signal Lost (bit 17.10) ......................................................... 93
100Base PLL Lock Error (bit 17.9) ......................................................................... 94
False Carrier (bit 17.8) ........................................................................................... 94
Invalid Symbol (bit 17.7) ........................................................................................ 94
Halt Symbol (bit 17.6) ............................................................................................ 95
Premature End (bit 17.5) ........................................................................................ 95
Auto-Negotiation Complete (bit 17.4) ..................................................................... 95
100Base-TX Signal Detect (bit 17.3) ..................................................................... 95
Jabber Detect (bit 17.2) ......................................................................................... 96
Remote Fault (bit 17.1) .......................................................................................... 96
Link Status (bit 17.0) .............................................................................................. 96
Register 18: 10Base-T Operations Register .......................................................... 97
Remote Jabber Detect (bit 18.15) .......................................................................... 97
Polarity Reversed (bit 18.14) ................................................................................. 98
ICS Reserved (bits 18.13:6) ................................................................................... 98
Jabber Inhibit (bit 18.5) .......................................................................................... 98
ICS Reserved (bit 18.4) ......................................................................................... 98
Auto Polarity Inhibit (bit 18.3) ................................................................................. 98
SQE Test Inhibit (bit 18.2) ...................................................................................... 98
Link Loss Inhibit (bit 18.1) ...................................................................................... 99
Squelch Inhibit (bit 18.0) ........................................................................................ 99
Copyright © 2000, Integrated Circuit Systems, Inc.
All rights reserved.
Table of Contents
Title
6
Table of Contents
June, 2000
Page