CYP15G0401DXB-BGXC Cypress Semiconductor Corp, CYP15G0401DXB-BGXC Datasheet - Page 22

• Manufacturer Part Number: CYP15G0401DXB-BGXC
• Description: IC TXRX HOTLINK 256LBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: HOTlink II™r
• Type: Transceiverr

Specifications of CYP15G0401DXB-BGXC

• Package / Case: 256-LBGA Exposed Pad, 32-HLBGA
• Number Of Drivers/receivers: 4/4
• Protocol: Multiprotocol
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Product: PHY
• Data Rate: 1500 MBd
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current: 1.06 A
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CYP15G0401DX-EVAL - IC TXRX HOTLINK 256-BGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Document #: 38-02002 Rev. *L
local loopback, all transmit Serial Driver outputs are forced to
output a differential logic-1. This prevents local diagnostic
patterns from being broadcast to attached remote receivers.
Signal Detect/Link Fault
Each selected Line Receiver (i.e., that routed to the clock and
data recovery PLL) is simultaneously monitored for
All of these conditions must be valid for the Signal Detect block
to indicate a valid signal is present. This status is presented on
the LFIx (Link Fault Indicator) output associated with each
receive channel.
Table 12. Analog Amplitude Detect Valid Signal Levels
Analog Amplitude
While most signal monitors are based on fixed constants, the
analog amplitude level detection is adjustable. This allows
operation with highly attenuated signals, or in high-noise
environments. This adjustment is made through the SDASEL
signal, a three-level select
the detection of a valid signal at one of three levels, as listed
in Table 12. This control input affects the analog monitors for
all receive channels.
The Analog Signal Detect Monitors are active for the Line
Receiver selected by the associated INSELx input. When the
channel is configured for local loopback (LPEN = HIGH), no
line receivers are selected, and the LFIx output for each
channel reports only the receive VCO frequency out-of-range
and transition density status of the associated transmit signal.
When local loopback is active, the Analog Signal Detect
Monitors are disabled.
Transition Density
The Transition Detection logic checks for the absence of any
transitions spanning greater than six transmission characters
(60 bits). If no transitions are present in the data received on
a channel, the Transition Detection logic for that channel will
assert LFIx. The LFIx output remains asserted until at least
one transition is detected in each of three adjacent received
characters.
Range Controls
The Clock/Data Recovery (CDR) circuit includes logic to
monitor the frequency of the Phase Locked Loop (PLL)
Notes:
12. REFCLK has no phase or frequency relationship with the recovered clock(s) and only acts as a centering reference to reduce clock synchronization time. REFCLK
13. The peak amplitudes listed in this table are for typical waveforms that have generally 3 – 4 transitions for every ten bits. In a worse case environment the signals
14. When a disabled receive channel is re-enabled, the status of the associated LFIx output and data on the parallel outputs for the associated channel may be
• analog amplitude above limit specified by SDASEL
• transition density greater than specified limit
• range controller reports the received data stream within
• receive channel enabled
MID (Open) 280 mV p-p differential
SDASEL
normal frequency range (±1500 ppm)
must be within ±1500 PPM (±0.15%) of the remote transmitter’s PLL reference (REFCLK) frequency. Although transmitting to a HOTLink II receiver necessitates
the frequency difference between the transmitter and receiver reference clocks to be within ±1500-PPM, the stability of the crystal needs to be within the limits
specified by the appropriate standard when transmitting to a remote receiver that is compliant to that standard. For example, to be IEEE 802.3z Gigabit Ethernet
compliant, the frequency stability of the crystal needs to be within ±100 PPM.
may have a sign-wave appearance (highest transition density with repeating 0101...). Signal peak amplitudes levels within this environment type could increase
the values in the table above by approximately 100 mV.
indeterminate for up to 2 ms.
HIGH
LOW
140 mV p-p differential
420 mV p-p differential
Typical signal with peak amplitudes above
[5]
input, which sets the trip point for
[12]
[13]
Voltage Controlled Oscillator (VCO) used to sample the
incoming data stream. This logic ensures that the VCO
operates at, or near the rate of the incoming data stream for
two primary cases:
To perform this function, the frequency of the VCO is periodi-
cally sampled and compared to the frequency of the REFCLK
input. If the VCO is running at a frequency beyond ±1500 ppm
[12]
cally forced to the correct frequency (as defined by REFCLK,
SPDSEL, and TXRATE) and then released in an attempt to
lock to the input data stream. The sampling and relock period
of the Range Control is calculated as follows: RANGE
CONTROL SAMPLING PERIOD = (REFCLKPERIOD) *
(16000).
During the time that the Range Control forces the PLL VCO to
run at REFCLK*10 (or REFCLK*20 when TXRATE = HIGH)
rate, the LFIx output will be asserted LOW. While the PLL is
attempting to re-lock to the incoming data stream, LFIx may be
either HIGH or LOW (depending on other factors such as
transition density and amplitude detection) and the recovered
byte clock (RXCLKx) may run at an incorrect rate (depending
on the quality or existence of the input serial data stream).
After a valid serial data stream is applied, it may take up to one
RANGE CONTROL SAMPLING PERIOD before the PLL
locks to the input data stream, after which LFIx should be
HIGH.
Receive Channel Enabled
The CYP(V)(W)15G0401DXB contains four receive channels
that can be independently enabled and disabled. Each
channel can be enabled or disabled separately through the
BOE[7:0] inputs, as controlled by the RXLE latch-enable
signal. When RXLE is HIGH, the signals present on the
BOE[7:0] inputs are passed through the Receive Channel
Enable Latch to control the PLLs and logic of the associated
receive channel. The BOE[7:0] input associated with a specific
receive channel is listed in Table 10.
When RXLE is HIGH and BOE[x] is HIGH, the associated
receive channel is enabled to receive and recover a serial
stream. When RXLE is HIGH and BOE[x] is LOW, the
associated receive channel is disabled and powered down. If
a single channel of a bonded-pair or bonded-quad is disabled,
the other receive channels may not bond correctly. If the
disabled channel is selected as the master channel for
insert/delete or recovered clock select, these functions will not
work correctly. Any disabled channel indicates an asserted
LFIx output. When RXLE returns LOW, the values present on
the BOE[7:0] inputs are latched in the Receive Channel
Enable Latch, and remain there until RXLE returns HIGH to
open the latch again.
• when the incoming data stream resumes after a time in
• when the incoming data stream is outside the acceptable
which it has been “missing”
frequency range
as defined by the reference clock frequency, it is periodi-
[14]
CYW15G0401DXB
CYP15G0401DXB
CYV15G0401DXB
Page 22 of 53