FAN53418MX Fairchild Semiconductor, FAN53418MX Datasheet - Page 8

• Manufacturer Part Number: FAN53418MX
• Description: MOSFET & Power Driver ICs DC-DC MOSFET Driver Synchronous
• Manufacturer: Fairchild Semiconductor
• Type: Synchronous DC-DC MOSFET Driverr

Specifications of FAN53418MX

• Rise Time: 45 ns
• Fall Time: 30 ns
• Supply Voltage (min): 10.8 V
• Supply Current: 6 mA
• Maximum Power Dissipation: 1052 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Minimum Operating Temperature: - 65 C
• Number Of Drivers: 2
• Number Of Outputs: 2
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FAN53418
Theory of Operation
The FAN53418 is a dual MOSFET driver optimized for
driving two N-channel MOSFETs in a synchronous buck
converter topology. A single PWM input signal is all that is
required to properly drive the high-side and the low-side
MOSFETs. Each driver is capable of driving a 3nF load at
frequencies over 500kHz.
A more detailed description of the FAN53418 and its
features follows. Refer to the Internal Block Diagram.
Low-Side Driver
The low-side driver is designed to drive a ground-referenced
low R
driver is internally connected to the VCC supply and PGND.
When the driver is enabled, the driver’s output is 180 degrees
out of phase with the PWM input. When the FAN53418 is
disabled, the low-side gate is held low.
High-Side Driver
The high-side driver is designed to drive a floating low
R
high-side driver is developed by an external bootstrap supply
circuit, which is connected between the BST and SW pins.
The bootstrap circuit comprises a diode, D1, and bootstrap
capacitor, C
pin is at ground, so the bootstrap capacitor will charge up to
VCC through D1. When the PWM input goes high,
the high-side driver will begin to turn the high-side
MOSFET, Q1, on by pulling charge out of C
turns on, the SW pin will rise up to V
to V
hold Q1 on. To complete the cycle, Q1 is switched off by
pulling the gate down to the voltage at the SW pin. When the
low-side MOSFET, Q2, turns on, the SW pin is pulled to
ground. This allows the bootstrap capacitor to charge up to
V
The high-side driver’s output is in phase with the PWM
input. When the driver is disabled, the high-side gate is
held low.
Overlap Protection Circuit
The overlap protection circuit prevents both of the main
power switches, Q1 and Q2, from being on at the same time.
This is done to prevent shoot-through currents from flowing
through both power switches and the associated losses that
can occur during their on-off transitions. The overlap pro-
tection circuit accomplishes this by adaptively controlling
the delay from Q1’s turn off to Q2’s turn on, and by inter-
nally setting the delay from Q2’s turn off to Q1’s turn on.
To prevent the overlap of the gate drives during Q1’s turn off
and Q2’s turn on, the overlap circuit monitors the voltage at
the SW pin. When the PWM input signal goes low, Q1 will
begin to turn off (after a propagation delay), but before Q2
can turn on the overlap protection circuit waits for the volt-
age at the SW pin to fall from V
the SW pin has fallen to 1V, Q2 will begin turn on. By
8
DS(on)
CC
IN
again.
DS(on)
+V
N-channel MOSFET. The bias voltage for the
C(BST)
BST
N-channel MOSFETs. The bias to the low-side
. When the FAN53418 is starting up, the SW
, which is enough gate to source voltage to
IN
to 1V. Once the voltage on
IN
, forcing the BST pin
BST
. As Q1
waiting for the voltage on the SW pin to reach 1V, the over-
lap protection circuit ensures that Q1 is off before Q2 turns
on, regardless of variations in temperature, supply voltage,
gate charge, and drive current.
To prevent the overlap of the gate drives during Q2’s turn off
and Q1’s turn on, the overlap circuit provides a internal delay
that is set to 50ns. When the PWM input signal goes high,
Q2 will begin to turn off (after a propagation delay), but
before Q1 can turn on the overlap protection circuit waits for
the voltage at DRVL to drop to around 10% of V
the voltage at DRVL has reached the 10% point, the overlap
protection circuit will wait for a 20 ns typical propagation
delay. Once the delay period has expired, Q1 will begin
turn on.
Application Information
Supply Capacitor Selection
For the supply input (V
capacitor is recommended to reduce the noise and to supply
some of the peak currents drawn. Use a 4.7µF, low ESR
capacitor. Multilayer ceramic chip (MLCC) capacitors pro-
vide the best combination of low ESR and small size. Keep
the ceramic capacitor as close as possible to the FAN53418.
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor (C
and a diode, as shown in Figure 1. Selection of these
components can be done after the high-side MOSFET has
been chosen.
The bootstrap capacitor must have a voltage rating that is
able to handle twice the maximum supply voltage. A mini-
mum 50V rating is recommended. The capacitance is
determined using the following equation:
where Q
MOSFET, and ∆V
high-side MOSFET drive. For example, an FDD6696 has a
total gate charge of about 17nC. For an allowed droop of
200mV, the minimum required bootstrap capacitance is
85nF. A good quality 100nF X7R ceramic capacitor should
be used.
A small–signal diode can be used for the bootstrap diode
due to the ample gate drive voltage supplied by V
bootstrap diode must have a minimum 15V rating to with-
stand the maximum supply voltage. The average forward
current can be estimated by:
where f
controller. The peak surge current rating should be checked
in-circuit, since this is dependent on the source impedance of
the 12V supply and the ESR of C
MAX
GATE
is the maximum switching frequency of the
is the total gate charge of the high-side
I
F AVG
(
BST
C
BST
is the voltage droop allowed on the
)
CC
=
) of the FAN53418, a local bypass
Q
=
GATE
Q
----------------- -
∆V
GATE
BST
BST
×
f
.
MAX
REV. 1.0.0 6/11/03
CC
CC
. Once
. The
BST
(1)
(2)
)