PSB3186FV14XP Infineon Technologies, PSB3186FV14XP Datasheet - Page 62
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PSB3186FV14XP
Manufacturer Part Number
PSB3186FV14XP
Description
Manufacturer
Infineon Technologies
Datasheet
1.PSB3186FV14XP.pdf
(200 pages)
Specifications of PSB3186FV14XP
Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Compliant
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ISAC-SX TE
PSB 3186
Description of Functional Blocks
F7 Activated
The receiver has synchronized and detects info 4. All user channels are now conveyed
transparently to the IOM-2 interface.
To transfer user channels transparently to the S/T interface either the command AR8 or
AR10 has to be issued and the signal from remote side must be synchronous.
F8 Lost Framing
The receiver has lost synchronization in the states F6 or F7 respectively.
Unconditional States
Loop A Closed (internal or external)
The ISAC-SX loops back the transmitter to the receiver and activates by transmission of
info 3. The receiver has not yet synchronized.
For a non transparent internal loop the DIS_TX bit of register TR_CONF2 has to be set
to ’1’.
Loop A Activated (internal or external)
The receiver has synchronized to info 3. Data may be sent. The indication “AIL” is output
to indicate the activated state. If the loop is closed internally and the S/T line awake
detector detects any signal on the S/T interface, this is indicated by “RSY”.
Test Mode - SSP
Single alternating pulses are transmitted to the S/T-interface resulting in a frequency of
the fundamental mode of 2 kHz.
Test Mode - SCP
Continuous alternating pulses are transmitted to the S/T-interface resulting in a
frequency of the fundamental mode of 96 kHz.
Data Sheet
62
2003-01-30
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