NAND512W3A2DN6E Micron Technology Inc, NAND512W3A2DN6E Datasheet - Page 17

• Manufacturer Part Number: NAND512W3A2DN6E
• Manufacturer: Micron Technology Inc

Specifications of NAND512W3A2DN6E

• Cell Type: NAND
• Density: 512Mb
• Access Time (max): 12us
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 26b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 64M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Compliant

NAND512xxA2D, NAND01GxxA2C
4.5
4.6
Write protect
Write protect bus operations are used to protect the memory against program or erase
operations. When the Write Protect signal is Low the device will not accept program or erase
operations and so the contents of the memory array cannot be altered. The Write Protect
signal is not latched by Write Enable to ensure protection even during power-up.
Standby
When Chip Enable is High the memory enters standby mode, the device is deselected,
outputs are disabled and power consumption is reduced.
Table 5.
1. Only for x16 devices.
2. WP must be V
Table 6.
1. A8 is set Low or High by the 00h or 01h command, see
2. Any additional address input cycles is ignored.
3. Only for 1-Gbit devices.
Table 7.
1. A8 is don’t care in x16 devices.
2. Any additional address input cycle is ignored.
3. Only for 1-Gbit devices.
Command input
cycle
Bus operation
cycle
Bus
Address input
Bus
2
Write protect
3
1
4
2
3
Data output
1
4
nd
Data input
st
rd
th
nd
rd
th
st
Standby
I/O15
I/O8-
X
X
X
X
Bus operations
Address insertion, x8 devices
Address insertion, x16 devices
I/O7
A16
A24
V
A7
IH
IL
when issuing a program or erase command.
V
V
V
V
V
E
X
I/O7
A16
A24
IH
IL
IL
IL
IL
V
A7
IL
I/O6
A15
A23
V
A6
IL
V
AL
V
V
V
X
X
IH
IL
IL
IL
I/O6
A15
A23
V
A6
IL
V
I/O5
CL
V
V
V
A14
A22
V
A5
X
X
IH
IL
IL
IL
IL
I/O5
A14
A22
Falling
V
A5
V
V
V
IL
R
X
X
IH
IH
IH
I/O4
A13
A21
V
A4
(1)(2)
IL
(1)(2)
Rising
Rising
Rising
Section 6.1: Pointer
I/O4
A13
A21
V
V
W
A4
X
X
IH
IL
I/O3
A12
A20
V
A3
WP
X
V
IL
X
X
X
X
(2)
IL
I/O3
A12
A20
V
A3
IL
Data output
I/O0 - I/O7
Command
Data input
I/O2
Address
A11
A19
operations.
V
A2
IL
I/O2
A11
A19
V
X
X
A2
IL
A26
I/O1
A10
A18
A1
A26
Bus operations
I/O1
A10
A18
A1
I/O8 - I/O15
(3)
Data output
(3)
Data input
X
X
X
X
I/O0
A17
A25
I/O0
A0
A9
A17
A25
A0
A9
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