NAND512W3A2DN6E Micron Technology Inc, NAND512W3A2DN6E Datasheet - Page 6

• Manufacturer Part Number: NAND512W3A2DN6E
• Manufacturer: Micron Technology Inc

Specifications of NAND512W3A2DN6E

• Cell Type: NAND
• Density: 512Mb
• Access Time (max): 12us
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 26b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 64M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Compliant

Description
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Description
The NAND flash 528-byte/264-word page is a family of non-volatile flash memories that
uses the single level cell (SLC) NAND technology. It is referred to as the small page family.
The NAND512xxA2D and NAND01GxxA2C devices have a density of 512 Mbits and 1 Gbit,
respectively. They operate with either a 1.8 V or 3 V voltage supply. The size of a page is
either 528 bytes (512 + 16 spare) or 264 words (256 + 8 spare) depending on whether the
device has a x8 or x16 bus width.
The address lines are multiplexed with the data input/output signals on a multiplexed x8 or
x16 input/output bus. This interface reduces the pin count and makes it possible to migrate
to other densities without changing the footprint.
To extend the lifetime of NAND flash devices it is mandatory to implement an error
correction code (ECC). The use of ECC correction allows to achieve up to 100,000
program/erase cycles for each block. A write protect pin is available to give a hardware
protection against program and erase operations.
The devices feature an open-drain ready/busy output that can be used to identify if the
program/erase/read (P/E/R) controller is currently active. The use of an open-drain output
allows the ready/busy pins from several memories to be connected to a single pull-up
resistor.
A Copy Back command is available to optimize the management of defective blocks. When
a page program operation fails, the data can be programmed in another page without having
to resend the data to be programmed.
The NAND512xxA2D devices are available in the TSOP48 (12 x 20 mm) and VFBGA63
(9 x 11 x 1.05 mm) packages while the NAND01GxxA2C devices are only available in the
TSOP48 (12 x 20 mm) package.
The NAND512xxA2D and NAND01GxxA2C devices are available in two different versions:
and come with two security features:
For more details about these security features, contact your nearest Numonyx sales office.
For information on how to order these options refer to
scheme. Devices are shipped from the factory with block 0 always valid and the memory
content bits, in valid blocks, erased to ’1’.
Table 2: Product description
in the family.
No option (Chip Enable ‘care’, sequential row read enabled): the sequential row read
feature allows to download up to all the pages in a block with one read command and
addressing only the first page to read
With Chip Enable ‘don’t care’ feature. This enables the sharing of the bus between
more active memories that are simultaneously active as Chip Enable transitions during
latency do not stop read operations. Program and erase operations are not interrupted
by Chip Enable transitions.
OTP (one time programmable) area, which is a restricted access area where sensitive
data/code can be stored permanently. The access sequence and further details about
this feature are subject to an NDA (non disclosure agreement)
Serial number (unique identifier), which enables each device to be uniquely identified. It
is subject to an NDA and is, therefore, not described in the datasheet.
lists the part numbers and other information for all the devices
Table 24: Ordering information
NAND512xxA2D, NAND01GxxA2C