FIN1026MTCX Fairchild Semiconductor, FIN1026MTCX Datasheet
FIN1026MTCX
Manufacturer Part Number
FIN1026MTCX
Description
IC RECEIVER 3.3V LVDS HS 14TSSOP
Manufacturer
Fairchild Semiconductor
Type
Receiverr
Datasheet
1.FIN1026MTC.pdf
(5 pages)
Specifications of FIN1026MTCX
Number Of Drivers/receivers
0/2
Protocol
LVDS
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Package / Case
14-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
FIN1026MTCX
FIN1026MTCXTR
FIN1026MTCXTR
© 2002 Fairchild Semiconductor Corporation
FIN1026MTC
FIN1026
3.3V LVDS 2-Bit High Speed Differential Receiver
General Description
This dual receiver is designed for high speed interconnects
utilizing Low Voltage Differential Signaling (LVDS) technol-
ogy. The receiver translates LVDS levels, with a typical dif-
ferential input threshold of 100mV, to LVTTL signal levels.
LVDS provides low EMI at ultra low power dissipation even
at high frequencies. This device is ideal for high speed
transfer of clock and data.
The FIN1026 can be paired with its companion driver, the
FIN1025, or any other LVDS driver.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Order Number
Package Number
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
DS500784
Features
Pin Descriptions
Truth Table
H
L
X
Z
Fail Safe
Greater than 400Mbs data rate
Flow-through pinout simplifies PCB layout
3.3V power supply operation
0.4ns maximum differential pulse skew
2.5ns maximum propagation delay
Low power dissipation
Power-Off protection
Fail safe protection for open-circuit, shorted and termi-
nated non-driven input conditions
Meets or exceeds the TIA/EIA-644 LVDS standard
14-Lead TSSOP package saves space
LOW Logic Level
Don’t Care
High Impedance
HIGH Logic Level
L or Open
R
R
R
OUT1
Package Description
Pin Name
EN
IN1
IN1
H
H
H
X
Open, Shorted, Terminated
GND
V
EN
EN
NC
, R
, R
, R
CC
OUT2
IN2
IN2
L or Open
L or Open
L or Open Fail Safe Condition
EN
H
X
Inputs
LVTTL Data Outputs
Non-Inverting LVDS Inputs
Inverting LVDS Inputs
Driver Enable Pin
Inverting Driver Enable Pin
Power Supply
Ground
No Connect
R
H
L
X
X
IN
June 2002
Revised June 2002
Description
R
www.fairchildsemi.com
H
L
X
X
IN
Outputs
R
OUT
H
H
L
Z
Z
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Datasheet:
FIN1026MTCX Summary of contents
Page 1
... Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram © 2002 Fairchild Semiconductor Corporation Features Greater than 400Mbs data rate Flow-through pinout simplifies PCB layout 3 ...
Page 2
Absolute Maximum Ratings Supply Voltage ( LVDS DC Input Voltage ( LVTTL DC Input Voltage ( Output Voltage (V ) OUT DC Output Current ( Storage Temperature Range (T ) STG ...
Page 3
AC Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified Symbol Parameter t Propagation Delay LOW-to-HIGH PLH t Propagation Delay HIGH-to-LOW PHL t Output Rise Time (20% to 80%) TLH t Output Fall Time (80% to 20%) ...
Page 4
FIGURE 2. LVDS Input to LVTTL Output AC Waveforms Voltage Waveforms Enable and Disable Times FIGURE 3. LVTTL Outputs Test Circuit and AC Waveforms www.fairchildsemi.com Test Circuit for LVTTL Outputs 4 ...
Page 5
Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...