M24C08-RMC6TG STMicroelectronics, M24C08-RMC6TG Datasheet - Page 13

• Manufacturer Part Number: M24C08-RMC6TG
• Description: 8KBIT SERIAL I2C BUS EEPROM
• Manufacturer: STMicroelectronics

Specifications of M24C08-RMC6TG

• Lead Free Status / Rohs Status: Compliant

M24C16, M24C08, M24C04, M24C02, M24C01
3.6
Figure 7.
Write operations
Following a Start condition the bus master sends a device select code with the Read/Write
bit (RW) reset to 0. The device acknowledges this, as shown in
address byte. The device responds to the address byte with an acknowledge bit, and then
waits for the data byte.
When the bus master generates a Stop condition immediately after a data byte Ack bit (in
the “10
cycle is triggered. A Stop condition at any other time slot does not trigger the internal write
cycle.
After the Stop condition, the t
the device internal address counter is automatically incremented, to point to the next byte
address after the last one that was modified. During the internal Write cycle,
Serial Data (SDA) is disabled internally, and the device does not respond to any request.
If the Write Control (WC) input is driven High, the Write instruction is not executed and the
corresponding data bytes are not acknowledged as shown in
WC
Byte Write
WC
Page Write
WC (cont'd)
Page Write
(cont'd)
th
bit” time slot), either at the end of a Byte Write or a Page Write, the internal write
Write mode sequences with WC = 1 (data write inhibited)
NO ACK
Dev select
Dev select
w
Data in N
Doc ID 5067 Rev 17
delay, and the successful completion of a Write operation,
R/W
R/W
ACK
ACK
NO ACK
Byte address
Byte address
ACK
ACK
Data in 1
Data in
NO ACK
NO ACK
Figure
Figure
Data in 2
7.
8, and waits for an
NO ACK
Device operation
Data in 3
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