M24C08-RMC6TG STMicroelectronics, M24C08-RMC6TG Datasheet - Page 16

• Manufacturer Part Number: M24C08-RMC6TG
• Description: 8KBIT SERIAL I2C BUS EEPROM
• Manufacturer: STMicroelectronics

Specifications of M24C08-RMC6TG

• Lead Free Status / Rohs Status: Compliant

Device operation
3.6.3
16/38
Figure 9.
Minimizing system delays by polling on ACK
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory cells. The maximum Write time (t
shown in
can be used by the bus master.
The sequence, as shown in
●
●
●
First byte of instruction
with RW = 0 already
decoded by the device
Initial condition: a Write cycle is in progress.
Step 1: the bus master issues a Start condition followed by a device select code (the
first byte of the new instruction).
Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
Table
Write cycle polling flowchart using ACK
15, but the typical time is shorter. To make use of this, a polling sequence
ReStart
Stop
NO
Figure
NO
Doc ID 5067 Rev 17
Start condition
Device select
addressing the
with RW = 0
in progress
operation is
Write cycle
Returned
memory
9, is:
ACK
Next
YES
Write operation
Write operation
Continue the
Data for the
M24C16, M24C08, M24C04, M24C02, M24C01
YES
NO
and Receive ACK
Send Address
condition
Start
Random Read operation
Device select
Continue the
with RW = 1
YES
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w
) is