ADV7343BSTZ Analog Devices Inc, ADV7343BSTZ Datasheet - Page 40

• Manufacturer Part Number: ADV7343BSTZ
• Description: IC ENCODER VIDEO W/DAC 64-LQFP
• Manufacturer: Analog Devices Inc
• Type: Video Encoderr

Specifications of ADV7343BSTZ

• Applications: DVD, Blu-Ray
• Voltage - Supply, Analog: 3.3V
• Voltage - Supply, Digital: 1.8V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Supply Voltage Range: 1.71V To 1.89V
• Operating Temperature Range: -40°C To +85°C
• Tv / Video Case Style: LQFP
• No. Of Pins: 64
• Svhc: No SVHC (18-Jun-2010)
• Operating Temperature Max: 85°C
• Operating: RoHS Compliant
• Input Format: Digital
• Output Format: Analogue
• Dac Resolution: 11bit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADV7342/ADV7343
SR7 to
SR0
0x88
0x89
1
Table 30. Register 0x8A to Register 0x98
SR7 to
SR0
0x8A
When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the selected standard. When set to 1, the
horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so.
Register
SD Mode
Register 7
SD Mode
Register 8
Register
SD Timing Register 0
Bit Description
Reserved
SD noninterlaced mode
SD double buffering
SD input format
SD digital noise reduction
SD gamma correction enable
SD gamma correction curve select
SD undershoot limiter
Reserved
SD black burst output on DAC luma
SD chroma delay
Reserved
Bit Description
SD slave/master mode
SD timing mode
Reserved
SD luma delay
SD minimum luma value
SD timing reset
Rev. A | Page 40 of 104
7
0
1
0
1
7
0
6
0
1
0
5
0
1
0
0
1
1
6
0
1
Bit Number
4
0
0
1
1
0
1
0
1
5
0
0
1
1
3
1
0
1
1
0
0
Bit Number
4
0
1
0
1
2
0
1
0
3
1
1
0
1
0
0
1
1
1
0
0
0
1
0
1
2
0
0
1
1
Register Setting
Disabled.
Enabled.
Disabled.
Enabled.
8-bit YCbCr input.
16-bit YCbCr input.
16-bit RGB input.
Reserved.
Disabled.
Enabled.
Disabled.
Enabled.
Gamma correction Curve A.
Gamma correction Curve B.
Disabled.
−11 IRE.
−6 IRE.
−1.5 IRE.
0 must be written to this bit.
Disabled.
Enabled.
Disabled.
Four clock cycles.
Eight clock cycles.
Reserved.
0 must be written to these bits.
1
0
1
0
1
0
0
1
Register Setting
Slave mode.
Master mode.
Mode 0.
Mode 1.
Mode 2.
Mode 3.
No delay.
Two clock cycles.
Four clock cycles.
Six clock cycles.
−40 IRE.
−7.5 IRE.
Normal operation .
Freezes the counters;
this bit must be set
back to zero in order to
reset the counters and
resume operation.
Reset
Value
0x00
0x00
Reset
Value
0x08