ADV7343BSTZ Analog Devices Inc, ADV7343BSTZ Datasheet - Page 79

• Manufacturer Part Number: ADV7343BSTZ
• Description: IC ENCODER VIDEO W/DAC 64-LQFP
• Manufacturer: Analog Devices Inc
• Type: Video Encoderr

Specifications of ADV7343BSTZ

• Applications: DVD, Blu-Ray
• Voltage - Supply, Analog: 3.3V
• Voltage - Supply, Digital: 1.8V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Supply Voltage Range: 1.71V To 1.89V
• Operating Temperature Range: -40°C To +85°C
• Tv / Video Case Style: LQFP
• No. Of Pins: 64
• Svhc: No SVHC (18-Jun-2010)
• Operating Temperature Max: 85°C
• Operating: RoHS Compliant
• Input Format: Digital
• Output Format: Analogue
• Dac Resolution: 11bit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

INTERNAL TEST PATTERN GENERATION
SD TEST PATTERNS
The ADV7342/ADV7343 are able to internally generate SD
color bar and black bar test patterns. For this function, a
27 MHz clock signal must be applied to the CLKIN_A pin.
The register settings in Table 62 are used to generate an SD
NTSC 75% color bar test pattern. CVBS output is available on
DAC 4, S-Video (Y-C) output is on DAC 5 and DAC 6, and
YPrPb output is on DAC 1 to DAC 3. On power-up, the
subcarrier frequency registers default to the appropriate values
for NTSC. All other registers are set as normal/default.
Table 62. SD NTSC Color Bar Test Pattern Register Writes
Subaddress
0x00
0x82
0x84
To generate an SD NTSC black bar test pattern, the settings
shown in Table 62 should be used with an additional write of
0x24 to Subaddress 0x02.
For PAL output of either test pattern, the same settings are used,
except that Subaddress 0x80 is programmed to 0x11, and the
subcarrier frequency registers are programmed as shown in
Table 63.
Table 63. PAL F
Subaddress
0x8C
0x8D
0x8E
0x8F
Note that, when programming the F
write the values in the sequence F
F
complete.
SC
value to be written is accepted only after the F
SC
Register Writes
Description
F
F
F
F
SC
SC
SC
SC
0
1
2
3
SC
0, F
SC
registers, the user must
SC
Setting
0xFC
0xC9
0x40
1, F
SC
2, F
SC
Setting
0xCB
0x8A
0x09
0x2A
SC
3 write is
3. The full
Rev. A | Page 79 of 104
ED/HD TEST PATTERNS
The ADV7342/ADV7343 are able to internally generate ED/HD
color bar, black bar, and hatch test patterns. For ED test patterns,
a 27 MHz clock signal must be applied to the CLKIN_A pin.
For HD test patterns, a 74.25 MHz clock signal must be applied
to the CLKIN_A pin.
The register settings in Table 64 are used to generate an ED
525p hatch test pattern. YPrPb output is available on DAC 1 to
DAC 3. All other registers are set as normal/default.
Table 64. ED 525p Hatch Test Pattern Register Writes
Subaddress
0x00
0x01
0x31
To generate an ED 525p black bar test pattern, the settings
shown in Table 64 should be used with an additional write of
0x24 to Subaddress 0x02.
To generate an ED 525p flat field test pattern, the settings
shown in Table 64 should be used, except that 0x0D should be
written to Subaddress 0x31.
The Y, Cr, and Cb levels for the hatch and flat field test patterns
can be controlled using Subaddress 0x36, Subaddress 0x37, and
Subaddress 0x38, respectively.
For ED/HD standards other than 525p, the settings shown in
Table 64 (and subsequent comments) are used, except that
Subaddress 0x30, Bits[7:3] are updated as appropriate.
ADV7342/ADV7343
Setting
0x1C
0x10
0x05