HMP8117CNZ Intersil, HMP8117CNZ Datasheet

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... MARKING (°C) HMP8117CN HMP8117CN PQFP HMP8117CNZ HMP8117CNZ PQFP (Note 1) HMPVIDEVAL/ISA Evaluation Board: ISA Frame Grabber (Note 3) NOTES: 1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations ...

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Functional Block Diagram SEE ANALOG FRONT END BLOCK DIAGRAM EXTERNAL ANTI-ALIAS FILTER Y OUT CVBS1 INPUT CLAMP, MUX, CVBS2 COARSE AGC, DC-RESTORE CVBS3(Y) LCAP EXTERNAL C COARSE AGC ANTI-ALIAS DC-RESTORE FILTER CCAP SEE DIGITAL PROCESSING BLOCK DIAGRAM Y IN YIN[7:0] ...

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Analog Front End Block Diagram (EXTERNAL) (INTERNAL CLAMP) VAA 1.75V INPUT TO + nmos - 1.0μF VIDEO MUX # 75 PIN 50μA 1.0μF VID1 CVBS1 CLAMP 7 1.0μF VID2 CVBS2 CLAMP 6 1.0μF Y_IN CVBS3(Y) CLAMP ...

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Digital Processing Block Diagram CLK2 FREQ SELECT (24.54, 27.0 or 29.5MHz) CHROMA CHROMA PLL LOOP PLL NCO FILTER CLK2 TO 4FSC RATIO 4FSC CLOCK CHROMA DATA C[7:0] LINE M DELAY C, CVBS U COMB X FILTER INPUT SAMPLE RATE CONVERTER ...

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Introduction The HMP8117 is designed to decode baseband composite or S-video NTSC and PAL signals, and convert them to either digital YCbCr or RGB data. In addition to performing the basic decoding operations, these devices include hardware to decode different ...

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Input Signal Detection If no input video signal is detected for 16 consecutive line periods, nominal video timing is generated for the previously detected or programmed video standard. A maskable interrupt is provided for the condition of “Input Signal Loss” ...

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Use of a PLL to generate a “Line Locked” CLK2 input based on the input video is not recommend. (See the following section.) Cycle Slipping and Real-Time Pixel Jitter The decoder’s digital PLL allows it to maintain lock and ...

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Y data. This may make a noisy image more pleasing to the user, although softer. Coring of the high-frequency Y data may be done to reduce low-level high frequency noise. Coring of the Y data may also be ...

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R′B′ < 0.0812*31, G′ < 0.0812* (31)((R′/31)/4. (63)((G′/63)/4. (31)((B′/31)/4.5) for R′B′ >= 0.0812*31, G′ >= 0.0812* (31)(((R′/31) + 0.099)/1.099 (63)(((G′/63) + 0.099)/1.099 (31)(((B′/31) ...

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NTSC(M) LINE# 262 263 PAL(M) LINE# 259 260 VIDEO INPUT HSYNC VSYNC FIELD LINE # 621 622 623 VIDEO INPUT HSYNC VSYNC FIELD ‘EVEN’ FIELD LINE # 309 310 311 VIDEO INPUT HSYNC VSYNC FIELD ‘ODD’ FIELD BLANK and DVALID ...

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NTSC M LINES NOT ACTIVE 240 ACTIVE LINES PER FIELD (LINES 23-262) 480 ACTIVE LINES/FRAME (NTSC, PAL M) LINES 263 - 284 NOT ACTIVE 240 ACTIVE LINES PER FIELD (LINES 285 - 524) NOT ACTIVE TOTAL PIXELS ...

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Pixel Output Port Pixel data is output via the P0-P15 pins. Refer to Table 4 for the output pin definition as a function of the output mode. Refer to the section “CYCLE SLIPPING AND REAL-TIME PIXEL JITTER” for PLL and ...

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CLK DVALID BLANK P15- P7-P0 Cb0 t DVLD NOTES the first active luminance pixel data of a line cycle due to the 4:2:2 subsampling. 10. BLANK is asserted per Figure 7. FIGURE 10. ...

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CLK DVALID P15-P8 P7-P0 NOTES: 12 the first active luminance pixel of a line the 4:2:2 subsampling. 13. BLANK is asserted per Figure 7. 14. DVALID is asserted for every valid pixel during both active ...

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CLK DVALID BLANK P[15- DVLD NOTES: 17 the first active luminance pixel data of a line every cycle due to the 4:2:2 subsampling. Pixel data is not output during the blanking period. 18. ...

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CAPTIONING DISABLED ON BOTH LINES In this case, any caption data present is ignored. The Caption odd field Read status bit and the Caption even field Read status bit are always a “0”. ODD FIELD CAPTIONING In this case, any ...

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ODD AND EVEN WSS WSS data present on line 20 (or line the PAL modes) is captured into a shift register then transferred to the WSS_ODD_A and WSS_ODD_B registers. WSS data present on line 283 (or ...

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TABLE 7. OUTPUTTING THE SLICED WSS DATA AS BT.656 ANCILLARY DATA PIXEL OUTPUT P15 Preamble Data ID P14 Data Block Number P14 Data Word Count P14 WSS Data P14 P14 P14 P14 WSS CRC P14 Data P14 ...

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CLOCK RUN-IN NOTES: 31. The MSB is bit number: 271 for system C, 279 for system B 525-line and 343 for system B 625-line. 32. The clock run- bits wide for both systems and is not included in ...

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During PAL ( operation, the first possible C line of VBI data are lines 6 and 318, and the last possible TABLE 9. OUTPUTTING RTCI AS BT.656 ANCILLARY DATA PIXEL INPUT Preamble Data ...

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In order to perform a read from a specific control register 2 within the HMP8117 bus write must first be performed to properly setup the address register. Then bus read can be performed ...

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Control Registers R SUB- ADDRESS CONTROL REGISTER 00 Product Input Format H 02 Output Format H 03 Output Control H 04 Genlock Control H 05 Analog Input Control H 06 Color Processing H 08 Luma Processing H ...

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BIT NUMBER FUNCTION 7-0 Product ID This 8-bit register specifies the last two digits of the product number. Data written to this read- only register is ignored. BIT NUMBER FUNCTION 7 Reserved 6-5 Video Timing These bits are read only ...

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BIT NUMBER FUNCTION 7 Video Data This bit is used to enable the P0-P15 outputs. Output Enable 0 = Outputs 3-stated Outputs enabled 6 Video Timing This bit is used to enable the HSYNC, VSYNC, BLANK, FIELD, VBIVALID, ...

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TABLE 16. ANALOG INPUT CONTROL REGISTER BIT NO. FUNCTION 7-6 Lock Loss If bits 5-4 do not equal “01”, these bits indicate what mode the AGC circuitry will be after loss of Video Gain sync. If bits 5-4 equal “01”, ...

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BIT NO. FUNCTION 7-6 Y Filtering The chroma trap filter may be used to remove any residual color subcarrier information from the Select Y channel. During S-video operation, it should be disabled. During PAL operation, it should be enabled. The ...

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TABLE 20. SLICED VBI DATA OUTPUT REGISTER BIT NO. FUNCTION 7 Sliced Closed If set to “1”, this bit enables output of sliced closed captioning via BT.656 ancillary data. Caption BT.656 Closed captioning must be enabled by the Sliced VBI ...

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BIT NO. FUNCTION 7 Vertical Lock This bit is read-only. Data written to this bit is ignored. Status If set to “1”, the decoder is vertically locked to the input signal. 6 Horizontal Lock This bit is read-only. Data written ...

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BIT NO. FUNCTION 7 Genlock Loss If set to “1”, this bit indicates the interrupt request was due to a loss of genlock. Interrupt Status To clear the interrupt request, a “1” must be written to this bit. 6 Input ...

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BIT NO. FUNCTION 7-0 Raw VBI Start Count Specifies the start of the raw VBI data sampling window in two CLK2 period steps from the leading edge of HSYNC. TABLE 27. RAW VBI STOP COUNT LSB REGISTER BIT NO. FUNCTION ...

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MASK MASK_18_16 (Register = Default) (Reg REGISTER BIT Mask Bit NTSC (Odd) Line NTSC (Even) Line# 290 289 288 PAL (Odd) Line PAL (Even) Line# ...

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BIT NO. FUNCTION 7-0 Video Gain Adjust This register is enabled by the selection of “fixed gain control” mode in the Analog Input Control register 05 digital gain factor which is applied to both Luma and Chroma input channels. The ...

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BIT NO. FUNCTION 7 Software Reset When this bit is set to 1, the entire device except the I like the RESET input going active. The software reset will initialize all register bits to their reset state. Once set this ...

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TABLE 45. CLOSED CAPTION_EVEN_B DATA REGISTER BIT NO. FUNCTION 15-8 Even Field If even field captioning is enabled and present, this register is loaded with the second eight bits Caption Data of caption data on line 281, 284, or 335. ...

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BIT NO. FUNCTION 7-6 Reserved 5-0 Even Field If even field WSS is enabled and present during NTSC operation, this register is loaded with the WSS CRC Data six bits of CRC information on line 283 always a ...

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BIT NO. FUNCTION 7-0 Negate BLANK This 8-bit register specifies the line number to negate BLANK each field. Output Signal For NTSC operation, it occurs on line ( odd fields and line (n + 268) on even ...

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TABLE 62. PROGRAMMABLE FRACTIONAL GAIN BIT NO. FUNCTION 7-6 Reserved Set Select PFG Enable Set to “1” to enable the recommended PFG value in bits 4-0 below. 4-0 PFG Programmable Fractional Gain (PFG). When enabled by ...

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Pinout AGND VAA AGND CVBS3(Y) CVBS2 CVBS1 Y AGND AGND VAA VAA AGND AGND A/D_TEST AGND AGND AGND AGND AGND Pin Descriptions PIN PIN NAME NUMBER I/O PASSIVE CVBS1 CVBS2, 75Ω Term, CVBS3(Y) I 1μF AC-coupled YOUT ...

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Pin Descriptions (Continued) PIN PIN NAME NUMBER I/O PASSIVE LCAP AGND CCAP AGND P0-P15 42, 43, 45, 47-51, 54-58, O 60, 63, 64 HSYNC 71 O 10kΩ Pullup VSYNC 70 O 10kΩ Pullup FIELD ...

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Applications Information Direct Interface to Video Encoders Direct interface to a video encoder will induce pixel jitter in the output video and is therefore not recommended as a primary data interface. The jitter will occur with all decoder output formats, ...

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... Related Application Notes Application Notes are also available on the Intersil Multimedia web site at http://www.intersil.com/mmedia. AN9644: Composite Video Separation Techniques AN9716: Wide Screen Signalling AN9717: YCbCr to RGB Considerations AN9728: BT.656 Video Interface for ICs AN9806: Advantages of the HMP8117 Videolyzer Operation EXTERNAL 75Ω ...

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Absolute Maximum Ratings Digital Supply Voltage (V to GND 7.0V CC Analog Supply Voltage (VAA to GND ...

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Electrical Specifications PARAMETER Input Leakage Current Input/Output Capacitance AC CHARACTERISTICS: DIGITAL I/O (EXCEPT I CLK2 Frequency CLK2 Waveform Symmetry CLK2 Pulse Width High CLK2 Pulse Width Low Data and Control Setup Time Data and Control Hold ...

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Electrical Specifications PARAMETER GENLOCK PERFORMANCE Horizontal Locking Time Long-Term horizontal Sync Lock Range Number of Missing Horizontal Syncs Before Lost Lock Declared Number of Missing Vertical Syncs Before Lost Lock Declared Long-Term Color Subcarrier Lock Range ...

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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...