PCA9539D,118 NXP Semiconductors, PCA9539D,118 Datasheet
PCA9539D,118
Specifications of PCA9539D,118
935277297118
PCA9539D-T
Related parts for PCA9539D,118
PCA9539D,118 Summary of contents
Page 1
... Purpose parallel Input/Output (GPIO) expansion with interrupt and reset for 2 I C-bus/SMBus applications and was developed to enhance the NXP Semiconductors family of I I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc. The PCA9539; PCA9539R consists of two 8-bit configuration (input or output selection), input, output and polarity inversion (active HIGH or active LOW operation) registers ...
Page 2
... NXP Semiconductors I Active LOW interrupt output I Active LOW reset input I Low standby current I Noise filter on SCL/SDA inputs I No glitch on power-up I Internal power-on reset I 16 I/O pins which default to 16 inputs 400 kHz clock frequency I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per ...
Page 3
... NXP Semiconductors 4. Block diagram A0 A1 SCL SDA V DD RESET V SS Fig 1. PCA9539_PCA9539R_5 Product data sheet 2 16-bit I C-bus and SMBus low power I/O port with interrupt and reset PCA9539 PCA9539R 2 I C-BUS/SMBus CONTROL INPUT FILTER POWER-ON RESET Remark: All I/Os are set to inputs at reset. ...
Page 4
... NXP Semiconductors 5. Pinning information 5.1 Pinning RESET IO0_0 IO0_1 IO0_2 IO0_3 IO0_4 IO0_5 IO0_6 IO0_7 Fig 2. Fig 4. PCA9539_PCA9539R_5 Product data sheet 2 16-bit I C-bus and SMBus low power I/O port with interrupt and reset 1 24 INT SDA 3 22 SCL IO1_7 6 19 IO1_6 ...
Page 5
... NXP Semiconductors 5.2 Pin description Table 3. Symbol INT A1 RESET IO0_0 IO0_1 IO0_2 IO0_3 IO0_4 IO0_5 IO0_6 IO0_7 V SS IO1_0 IO1_1 IO1_2 IO1_3 IO1_4 IO1_5 IO1_6 IO1_7 A0 SCL SDA V DD [1] HVQFN24 package die supply ground is connected to both V be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board ...
Page 6
... NXP Semiconductors 6. Functional description Refer to 6.1 Device address Fig 5. PCA9539; PCA9539R device address 6.2 Registers 6.2.1 Command byte The command byte is the first byte to follow the address byte during a write transmission used as a pointer to determine which of the following registers will be written or read. ...
Page 7
... NXP Semiconductors 6.2.2 Registers 0 and 1: Input port registers This register is an input-only port. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by Register 3. Writes to this register have no effect. The default value ‘X’ is determined by the externally applied logic level. ...
Page 8
... NXP Semiconductors 6.2.5 Registers 6 and 7: Configuration registers This register configures the directions of the I/O pins bit in this register is set (written with ‘1’), the corresponding port pin is enabled as an input with high-impedance output driver bit in this register is cleared (written with ‘0’), the corresponding port pin is enabled as an output ...
Page 9
... NXP Semiconductors data from shift register data from shift register configuration write pulse read pulse data from shift register write polarity Fig 6. Simplified schematic of I/Os 6.6 Bus transactions 6.6.1 Writing to the port registers Data is transmitted to the PCA9539; PCA9539R by sending the device address and setting the least signifi ...
Page 10
SCL slave address SDA START condition R/W write to port data out from port 0 data out from port 1 Fig 7. Write ...
Page 11
... NXP Semiconductors 6.6.2 Reading the port registers In order to read data from the PCA9539; PCA9539R, the bus master must first send the PCA9539; PCA9539R address with the least significant bit set to a logic 0 (see “PCA9539; PCA9539R device determines which register will be accessed. After a restart, the device address is sent again, but this time the least signifi ...
Page 12
INT INT t t v(INT_N) rst(INT_N) SCL R/W slave address I0.x SDA ...
Page 13
DATA 00 t h(D) data into port 1 DATA 10 INT t t v(INT_N) rst(INT_N) SCL R/W slave address I0.x SDA ...
Page 14
... NXP Semiconductors 6.6.3 Interrupt output The open-drain interrupt output is activated when one of the port pins change state and the pin is configured as an input. The interrupt is deactivated when the input returns to its previous state or the Input port register is read (see output cannot cause an interrupt. Since each 8-bit port is read independently, the interrupt caused by Port 0 will not be cleared by a read of Port 1 or the other way around ...
Page 15
... NXP Semiconductors 7.2 System configuration A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see SDA SCL ...
Page 16
... NXP Semiconductors 8. Application design-in information MASTER CONTROLLER SCL SDA INT RESET V SS Device address configured as 1110 100X for this example. IO0_0, IO0_2, IO0_3 configured as outputs. IO0_1, IO0_4, IO0_5 configured as inputs. IO0_6, IO0_7 and (IO1_0 to IO1_7) configured as inputs. ...
Page 17
... NXP Semiconductors 8.1 Minimizing I When the I/Os are used to control LEDs, they are normally connected to V resistor as shown about 1.2 V less than V I than V DD Designs needing to minimize current consumption, such as battery power applications, should consider maintaining the I/O pins greater than or equal to V Figure 17 than the LED supply voltage by at least 1 ...
Page 18
... NXP Semiconductors 10. Static characteristics Table 14. Static characteristics Symbol Parameter Supplies V supply voltage DD I supply current DD I standby current stb V power-on reset voltage POR Input SCL; input/output SDA V LOW-level input voltage IL V HIGH-level input voltage IH I LOW-level output current OL I leakage current ...
Page 19
... NXP Semiconductors [3] The total current sourced by all I/Os must be limited to 160 mA (80 mA for IO0_0 through IO0_7 and 80 mA for IO1_0 through IO1_7). 11. Dynamic characteristics Table 15. Dynamic characteristics Symbol Parameter f SCL clock frequency SCL t bus free time between a STOP and BUF START condition ...
Page 20
... NXP Semiconductors SDA t BUF t LOW SCL t HD;STA P S Fig 19. Definition of timing on the I START SCL SDA 30 % RESET IOn Fig 20. Definition of RESET timing in PCA9539 START SCL SDA 30 % RESET rec(rst) IOn Fig 21. Definition of RESET timing in PCA9539R PCA9539_PCA9539R_5 Product data sheet 2 16-bit I ...
Page 21
... NXP Semiconductors Fig 22. Expanded view of read input port register Fig 23. Expanded view of write to output port register protocol SCL SDA Fig 24. I PCA9539_PCA9539R_5 Product data sheet 2 16-bit I C-bus and SMBus low power I/O port with interrupt and reset SCL 2 1 SDA input ...
Page 22
... NXP Semiconductors 12. Test information Fig 25. Test circuitry for switching times Fig 26. Load circuit Table 16. Test t v(Q) PCA9539_PCA9539R_5 Product data sheet 2 16-bit I C-bus and SMBus low power I/O port with interrupt and reset V I PULSE GENERATOR R = load resistor load capacitance includes jig and probe capacitance. ...
Page 23
... NXP Semiconductors 13. Package outline SO24: plastic small outline package; 24 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 2.65 mm 0.25 0.1 2.25 0.012 0.096 0.1 inches 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
Page 24
... NXP Semiconductors TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
Page 25
... NXP Semiconductors HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 0.85 mm terminal 1 index area terminal 1 24 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
Page 26
... NXP Semiconductors 14. Handling information Inputs and outputs are protected against electrostatic discharge in normal handling. However completely safe you must take normal precautions appropriate to handling integrated circuits. 15. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “ ...
Page 27
... NXP Semiconductors • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 15.4 Reflow soldering Key characteristics in reflow soldering are: • ...
Page 28
... NXP Semiconductors Fig 30. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 16. Abbreviations Table 19. Acronym ACPI CBT CDM CMOS ESD FET FF GPIO HBM 2 I C-bus I/O ...
Page 29
... NXP Semiconductors 17. Revision history Table 20. Revision history Document ID Release date PCA9539_PCA9539R_5 20080728 • Modifications: • PCA9539_PCA9539R_4 20080519 PCA9539_3 20060921 PCA9539_2 20040930 (9397 750 14048) PCA9539_1 20040827 (9397 750 12898) PCA9539_PCA9539R_5 Product data sheet 2 16-bit I C-bus and SMBus low power I/O port with interrupt and reset ...
Page 30
... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
Page 31
... NXP Semiconductors 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . . 6 6.1 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Registers 6.2.1 Command byte . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2.2 Registers 0 and 1: Input port registers . . . . . . . 7 6 ...