PCA9539D,118 NXP Semiconductors, PCA9539D,118 Datasheet - Page 19

• Manufacturer Part Number: PCA9539D,118
• Description: IC I/O EXPANDER I2C 16B 24SOIC
• Manufacturer: NXP Semiconductors

Specifications of PCA9539D,118

• Package / Case: 24-SOIC (7.5mm Width)
• Interface: I²C, SMBus
• Number Of I /o: 16
• Interrupt Output: Yes
• Frequency - Clock: 400kHz
• Voltage - Supply: 2.3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Includes: POR
• Logic Family: PCA9539
• Number Of Lines (input / Output): 16.0 / 16.0
• Operating Supply Voltage: 2.3 V to 5.5 V
• Power Dissipation: 200 mW
• Operating Temperature Range: - 40 C to + 85 C
• Input Voltage: 5 V
• Logic Type: I2C, SMBus
• Maximum Clock Frequency: 400 KHz
• Mounting Style: SMD/SMT
• Number Of Input Lines: 16.0
• Number Of Output Lines: 16.0
• Output Current: 50 mA
• Output Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-1842-2; 935277297118; PCA9539D-T

NXP Semiconductors
[3]
11. Dynamic characteristics
Table 15.
[1]
[2]
[3]
[4]
[5]
[6]
PCA9539_PCA9539R_5
Product data sheet
Symbol
f
t
t
t
t
t
t
t
t
t
t
t
t
t
Port timing
t
t
t
Interrupt timing
t
t
RESET timing
t
t
t
SCL
BUF
HD;STA
SU;STA
SU;STO
VD;ACK
HD;DAT
VD;DAT
SU;DAT
LOW
HIGH
f
r
SP
v(Q)
su(D)
h(D)
v(INT_N)
rst(INT_N)
w(rst)
rec(rst)
rst
The total current sourced by all I/Os must be limited to 160 mA (80 mA for IO0_0 through IO0_7 and 80 mA for IO1_0 through IO1_7).
t
t
C
t
Resetting the device while actively communicating on the bus may cause glitches or errant STOP conditions.
Upon reset, the full delay will be the sum of t
VD;ACK
VD;DAT
v(Q)
b
= total capacitance of one bus line in pF.
measured from 0.7V
= minimum time for SDA data out to be valid following SCL LOW.
= time for acknowledgement signal from SCL LOW to SDA (out) LOW.
Parameter
SCL clock frequency
bus free time between a STOP and
START condition
hold time (repeated) START condition
set-up time for a repeated START
condition
set-up time for STOP condition
data valid acknowledge time
data hold time
data valid time
data set-up time
LOW period of the SCL clock
HIGH period of the SCL clock
fall time of both SDA and SCL signals
rise time of both SDA and SCL signals
pulse width of spikes that must be
suppressed by the input filter
data output valid time
data input set-up time
data input hold time
valid time on pin INT
reset time on pin INT
reset pulse width
reset recovery time
reset time
Dynamic characteristics
DD
on SCL to 50 % I/O output.
16-bit I
rst
and the RC time constant of the SDA bus.
2
Rev. 05 — 28 July 2008
C-bus and SMBus low power I/O port with interrupt and reset
Conditions
[5][6]
[1]
[2]
[3]
[3]
[4]
PCA9539; PCA9539R
Standard-mode
Min
300
250
150
400
4.7
4.0
4.7
4.0
0.3
4.7
4.0
0
0
1
4
0
-
-
-
-
-
-
I
2
C-bus
1000
Max
3.45
100
300
200
50
4
4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
20 + 0.1C
20 + 0.1C
Fast-mode I
Min
100
150
400
1.3
0.6
0.6
0.6
0.1
1.3
0.6
50
0
0
1
4
0
-
-
-
-
© NXP B.V. 2008. All rights reserved.
b
b
2
C-bus
Max
400
300
300
200
0.9
50
4
4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
19 of 31
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
s
s
s
s
s
s
s
s