PCA9539D,118 NXP Semiconductors, PCA9539D,118 Datasheet - Page 9

• Manufacturer Part Number: PCA9539D,118
• Description: IC I/O EXPANDER I2C 16B 24SOIC
• Manufacturer: NXP Semiconductors

Specifications of PCA9539D,118

• Package / Case: 24-SOIC (7.5mm Width)
• Interface: I²C, SMBus
• Number Of I /o: 16
• Interrupt Output: Yes
• Frequency - Clock: 400kHz
• Voltage - Supply: 2.3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Includes: POR
• Logic Family: PCA9539
• Number Of Lines (input / Output): 16.0 / 16.0
• Operating Supply Voltage: 2.3 V to 5.5 V
• Power Dissipation: 200 mW
• Operating Temperature Range: - 40 C to + 85 C
• Input Voltage: 5 V
• Logic Type: I2C, SMBus
• Maximum Clock Frequency: 400 KHz
• Mounting Style: SMD/SMT
• Number Of Input Lines: 16.0
• Number Of Output Lines: 16.0
• Output Current: 50 mA
• Output Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-1842-2; 935277297118; PCA9539D-T

NXP Semiconductors
PCA9539_PCA9539R_5
Product data sheet
6.6.1 Writing to the port registers
6.6 Bus transactions
Data is transmitted to the PCA9539; PCA9539R by sending the device address and
setting the least significant bit to a logic 0 (see
address”). The command byte is sent after the address and determines which register will
receive the data following the command byte.
The eight registers within the PCA9539; PCA9539R are configured to operate as four
register pairs. The four pairs are Input ports, Output ports, Polarity inversion ports, and
Configuration ports. After sending data to one register, the next data byte will be sent to
the other register in the pair (see
sent to Output port 1 (register 3), then the next byte will be stored in Output port 0
(register 2). There is no limitation on the number of data bytes sent in one write
transmission. In this way, each 8-bit register may be updated independently of the other
registers.
Fig 6. Simplified schematic of I/Os
configuration
write polarity
shift register
shift register
shift register
write pulse
read pulse
data from
data from
data from
pulse
pulse
write
At power-on reset, all registers return to default values.
configuration
register
D
CK
16-bit I
FF
Q
Q
2
Rev. 05 — 28 July 2008
C-bus and SMBus low power I/O port with interrupt and reset
output port
register
D
CK
Figure 7
FF
Q
and
PCA9539; PCA9539R
input port
register
polarity inversion
register
D
CK
D
CK
Figure
Figure 5 “PCA9539; PCA9539R device
FF
FF
Q
Q
8). For example, if the first byte is
Q1
Q2
© NXP B.V. 2008. All rights reserved.
output port
register data
V
I/O pin
V
input port
register data
to INT
polarity
inversion
register data
DD
SS
002aad723
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