PCA9539D,118 NXP Semiconductors, PCA9539D,118 Datasheet - Page 11

• Manufacturer Part Number: PCA9539D,118
• Description: IC I/O EXPANDER I2C 16B 24SOIC
• Manufacturer: NXP Semiconductors

Specifications of PCA9539D,118

• Package / Case: 24-SOIC (7.5mm Width)
• Interface: I²C, SMBus
• Number Of I /o: 16
• Interrupt Output: Yes
• Frequency - Clock: 400kHz
• Voltage - Supply: 2.3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Includes: POR
• Logic Family: PCA9539
• Number Of Lines (input / Output): 16.0 / 16.0
• Operating Supply Voltage: 2.3 V to 5.5 V
• Power Dissipation: 200 mW
• Operating Temperature Range: - 40 C to + 85 C
• Input Voltage: 5 V
• Logic Type: I2C, SMBus
• Maximum Clock Frequency: 400 KHz
• Mounting Style: SMD/SMT
• Number Of Input Lines: 16.0
• Number Of Output Lines: 16.0
• Output Current: 50 mA
• Output Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-1842-2; 935277297118; PCA9539D-T

NXP Semiconductors
PCA9539_PCA9539R_5
Product data sheet
Fig 9. Read from register
SDA
(cont.)
Remark: Transfer can be stopped at any time by a STOP condition.
S
START condition
S
(repeated)
START condition
6.6.2 Reading the port registers
1
1
1
slave address
1
1
slave address
1
In order to read data from the PCA9539; PCA9539R, the bus master must first send the
PCA9539; PCA9539R address with the least significant bit set to a logic 0 (see
“PCA9539; PCA9539R device
determines which register will be accessed. After a restart, the device address is sent
again, but this time the least significant bit is set to a logic 1. Data from the register
defined by the command byte will then be sent by the PCA9539; PCA9539R (see
Figure
the acknowledge clock pulse. After the first byte is read, additional bytes may be read but
the data will now reflect the information in the other register in the pair. For example, if you
read Input port 1, then the next byte read would be Input port 0. There is no limitation on
the number of data bytes received in one read transmission but the final byte received, the
bus master must not acknowledge the data.
0
0
1 A1 A0
1 A1 A0 1
acknowledge
9,
from slave
acknowledge
Figure 10
R/W
from slave
0
R/W
A
16-bit I
A
MSB
and
COMMAND BYTE
at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
2
upper byte of register
Rev. 05 — 28 July 2008
C-bus and SMBus low power I/O port with interrupt and reset
data from lower or
Figure
DATA (first byte)
address”). The command byte is sent after the address and
11). Data is clocked into the register on the falling edge of
acknowledge
from slave
LSB
A
A
acknowledge
from master
PCA9539; PCA9539R
(cont.)
MSB
lower byte of register
data from upper or
DATA (last byte)
no acknowledge
from master
LSB
© NXP B.V. 2008. All rights reserved.
NA
002aad727
P
STOP
condition
Figure 5
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